Samsung Electronics Co., Ltd.

Jung-Ik Oh

Ha-Na Kim

Daehyun Jang

Jongchul Park

Jong-Kyu Kim

Gwang-Hyun Baek

Kyoungsub Shin

Inho Kim

Kyoung-Sub Shin

Dae-hyun Jang

Dae-Hyun Jang

Hyun-woo Yang

Jaehun Seo

Sang-Kuk Kim

Seong-Soo Lee

Han-Na Cho

Kyungrae Byun

Seongsoo Lee

Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

Methods of forming staircase-shaped connection structures of three-dimensional semiconductor devices

Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas. The first gas contains a hydrogen element (H), and the second gas contains a source gas different from that of the first gas.

Methods of forming an interconnection line and methods of fabricating a magnetic memory device using the same

A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.

Semiconductor device having magnetic tunnel junction structure and method of forming the same

A method for forming a pattern, the method including forming an etch target layer on a substrate; patterning the etch target layer to form patterns; and performing a pre-oxidation trim process a plurality of times, the pre-oxidation trim process including performing an oxidation process to form an insulating layer on a sidewall of each of the patterns; and performing a sputter etch process to remove at least a portion of the insulating layer.

Method for forming patterns and method for manufacturing magnetic memory device using the same

A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.

Memory device and method of fabricating the same

A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.

Vertical memory devices and methods of manufacturing the same

Staircase-shaped connection structures of three-dimensional semiconductor devices

According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

Method of fabricating semiconductor devices having vertical cells

According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth.

Method of fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated using the same

A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

Growing community of inventors

Seongnam-si, South Korea

Jung-Ik Oh