Samsung Electronics Co., Ltd.

Jung-hyun Shin

Won-mo Park

Yong-hee Lee

Young-woo Seo

Young-hun Park

A semiconductor device includes a connection pad layer for securing a contact margin which is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. A device fabricated according to this structure yields improved punch-through and junction depth characteristics.

Semiconductor device with selectively patterned connection pad layer for

A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.

Method of manufacturing a semiconductor device having self aligned

Semiconductor device and manufacturing method thereof

A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation. In forming the second conductivity-type area, an additional insulating layer is formed, and using a mask pattern for exposing the second conductivity area, selectively and anisotropically etched so that the remaining insulating layer or the mask pattern for exposing the second conductivity-type area serves as an impurity-implantation preventing mask.

Growing community of inventors

Suwon, South Korea

Jung-hyun Shin