Samsung Electronics Co., Ltd.

Jung Hyuk Lee

Daewon Ha

Yoonjong Song

Gwan-Hyeob Koh

Kwangjin Lee

Seung Pil Ko

Shinhee Han

Daehwan Kang

Hyunsung Jung

Myoungsu Son

Kang Ho Lee

Gitae Jeong

Hyemin Shin

Kyung Min Lee

Jin Doo Kim

Min-Sun Keel

Kwang-woo Lee

Kyu-Rie Sim

Hoon Joo Na

Sang Kil Lee

Kil Ho Lee

Yong Sok Lee

Min Hee Kang

Hyung Sub Lim

Kyung Up Lim

Dae Shik Kim

Hye Min Shin

Nam Kyu Jun

Shin Hee Han

An image sensor including a variable resistance element is provided. The image sensor comprises first and second chips having first and second connecting structures; and a contact plug connecting the first and second chips. The first chip includes a photoelectric conversion element. The second chip includes a first variable resistance element. The contact plug extends from the first surface of the first semiconductor substrate to connect the first and second connecting structures.

Image sensor

A memory device includes a first nonvolatile memory including a resistive memory cell; and a controller. The controller may be configured to provide the first nonvolatile memory with a first data, a first program command, and a first address. The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command. The controller may be configured to compare the first data with the second data to detect a number of fail cells. When the number of detected fail cells is greater than a reference value, the controller may be configured to generate a third data obtained by inversing the first data, and provide the third data to the first nonvolatile memory. The first data may include an inversion flag bit.

Nonvolatile memory device having resistive memory cells and a controller to detect fail cells, and electronic device including the same

A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.

Test method for memory device, operation method of test device testing memory device, and memory device with self-test function

Test method for memory device, operating method of test device testing memory device, and memory device with self-test function

A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Semiconductor devices

Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

Memory device and programming method

A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.

Memory devices configured to prevent read failure due to leakage current into bit line

A drum washing machine and a control method thereof. The drum washing machine includes a cabinet, a tub including a first tub part and a second tub part, a drum, an inlet provided at one side of the second tub part and supplying condensed water, and at least one flow path provided on one surface from among the inner surfaces of the second tub part opposite the drum and guiding flow of the condensed water to increase a contact area between the condensed water supplied from the inlet and the second tub part. The drum washing machine improves the structure of the tub to effectively inject condensed water, and may thus increase condensing efficiency. Further, the drum washing machine improves the structures of the tub and the drying duct, and may thus prevent accumulation of lint and lowering of performance of the drum washing machine.

Drum washing machine

A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer.

Method of operating a nonvolatile memory by reprogramming failed cells using a reinforced program pulse in an idle state and memory system thereof

A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered.

Resistive memory device and sensing margin trimming method thereof

A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells.

Resistance change memory device and current trimming method thereof

A variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.

Resistive memory device capable of compensating for variations of bit line resistances

A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current.

Growing community of inventors

Hwaseong-si, South Korea

Jung Hyuk Lee