Samsung Electronics Co., Ltd.

Lg Chem, Ltd

Other

Korea Basic Science Institute

Lg-nortel Co., Ltd.

Wooshin Industrial Co., Ltd.

Samhyun Cns Co., Ltd.

Jung-Hwan Kim

Hun-Hyeoung Leam

Kwang-Chul Choi

Un-Byoung Kang

Hyun Namkoong

Yong-Seok Kim

Tae-Hyun Kim

Tae Hong Min

Seok-Woo Nam

Tea-Kwang Yu

Sunggil Kim

Chungsun Lee

Jai-Dong Lee

Young-sub You

Woong Hee Lee

Tae-Je Cho

Ji-Hoon Choi

Seulye Kim

Hyung-Sun Jang

Tae-Hong Min

Ki Eob Moon

Woo-Sung Lee

Hun-hyeong Lim

Jeon Il Lee

Jung-Seok Ahn

Jae-hyun Phee

Seyoung Jeong

Seogjin Yoon

Sang-Hoon Lee

Ki-Hyun Hwang

Ju-Il Choi

Jae-Ho Choi

Young-Seok Kim

Sun-Pil Youn

Hojin Lee

Taeje Cho

Hyun-Jung Song

Chung-Sun Lee

Young-bok Ju

Hyun-Jin Shin

Dongkyum Kim

Won-Jun Jang

Jung Geun Jee

Dong-Kyum Kim

Eun-Kyoung Choi

Woon-Seong Kwon

Minseung Yoon

Yong-Sun Lee

Jin-Woo Park

Donghan Kim

Sungjin Kim

Seung-Hwan Moon

Sung-Min Hwang

Sang-Hun Lee

Hyang Mok Lee

Ho-jin Lee

Sangwook Park

Yu-sin Yang

Chung-sam Jun

Yongjin Lee

Chang-Sub Lee

Kyu-Dong Jung

Sang-kil Lee

Yonghwan Kwon

Il Hwan Kim

Hyuekjae Lee

Sung-Woo Park

Chan-ho Park

Kyu-ha Lee

Dongchul Yoo

Young-Dae Kim

Yun-Hyeok Im

Jihwan Hwang

Hong-suk Kim

Bong-hyun Kim

Kwang-Jin Bae

Jun-Kyu Yang

Yong-Woo Hyung

Ju-Hwan Baek

Myoung Choul Choi

Tae-Hong Kim

Man-Sug Kang

Soo Min Park

Young Kun Jee

Jintae Noh

Seung-Mok Shin

HongSuk Kim

Gukhyon Yon

Hyung-gyu Lee

So-Young Lim

Yong-Gil Han

Cheol Woong Lee

Won-Seok Yoo

Soonkwang Jung

Guk-Hyon Yon

Hyuek-Jae Lee

Hanvit Yang

Taeeun Kim

Jung Kyu Woo

Jong-Phil Lee

Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

Semiconductor devices and electronic systems including the same

A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

Three-dimensional semiconductor devices

A semiconductor package includes a lower semiconductor chip having a first surface and a second surface, an upper semiconductor chip on the first surface, a first insulating layer between the first surface and the upper semiconductor chip, a second insulating layer between the first insulating layer and the upper semiconductor chip, and a connection structure penetrating the first insulating layer and the second insulating layer and being connected to the lower semiconductor chip and the upper semiconductor chip. The connection structure includes a first connecting portion and a second connecting portion, which are respectively disposed in the first insulating layer and the second insulating layer. A width of the second connecting portion is greater than a width of the first connecting portion. A thickness of the second connecting portion is greater than a thickness of the first connecting portion.

Semiconductor package

A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

Semiconductor device having a stack including electrodes vertically stacked on a substrate and electronic system including the same

A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

Three-dimensional semiconductor memory devices

Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

Three-dimensional semiconductor memory devices and methods of fabricating the same

A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

Vertical memory devices

Disclosed is a communication method that prevents excess message transmission and improves the efficiency of a communication system. The method includes transmitting a first connection request message for a service connection to a network by an electronic device, receiving a first connection reject message for the first connection request from the network, abstaining from retransmission of the connection request to the network based on the first connection reject message, determining whether an operation configured in the electronic device belongs to a condition set by the electronic device based on at least a portion of the abstinence operation, and when determining that the operation belongs to the condition, transmitting a second connection request message to the network.

Electronic device and communication method of electronic device

Provided are an apparatus for measuring an ionic mobility of a harmful material and a reference data obtaining method thereof. The method includes obtaining a measurement signal by detecting a charge of an ion between electrodes, obtaining a noise signal by insulating the electrodes from the ion, aligning the noise signal with the measurement signal, removing a part of the measurement signal aligned with the noise signal, and calculating reference data from a remaining part of the measurement signal.

Apparatus for measuring ion mobility of harmful material and reference data obtaining method of the same

A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Semiconductor devices and methods of manufacturing the same

Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

Initiator and method for debonding wafer supporting system

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Semiconductor device and method of fabricating the same

A method of manufacturing a filter pipe for vehicles which has an expanded tube portion with a different diameter at one side and is provided with a plurality of through holes formed along a circumferential direction includes: forming the plurality of through holes in a mother member; forming furrows at one end portion of the mother member; forming a planar member having the plurality of through holes and the furrows by a shearing process of the mother member; bending the planar member in a tubular shape and spreading the furrows to form an area where the furrows are formed in an expanded tube shape; and adhering both facing end portions of the planar member so as to form a body having the expanded tube portion at one side thereof.

Method of manufacturing filter pipe for vehicle and filter pipe for vehicle

Growing community of inventors

Seoul, South Korea

Jung-Hwan Kim