Samsung Electronics Co., Ltd.

Jung-hwan Choi

Young-jin Kim

Seung-Woon Lee

Tae-Soo Kim

Young-Soo Sohn

Sung-hee Kim

Kang-tae Kim

Seung-Jun Bae

Jung-Bae Lee

Kang-Tae Kim

Dae-wook Park

Sung-Hee Kim

Yun-Sang Lee

Jae-kwan Kim

Gyung-Su Byun

Jae-Yeol Lee

Tae-Sik Yang

Joong-hee Lee

Jae-young Chung

Jin-Hyun Kim

Seung-gil Jeon

Hong-Jun Park

Hee-young Seo

A method of displaying an application is provided. The method includes displaying an execution screen of a first application on a first area when the first application is executed, displaying the execution screen of the first application on a second area instead of on the first area when a second application is executed while the first application is executed, and displaying an execution screen of a second application on the first area.

Method and apparatus for displaying application

A method for controlling a display device that includes a touch screen is provided. The method includes establishing a plurality of window display spaces in the touch screen, wherein each of the plurality of window display spaces displays a window for running an application, displaying a launcher application in one of the plurality of window display spaces, the launcher application presenting at least one icon to run at least one application, receiving in the launcher application a new application run command to run a new application, and displaying a new window for running the new application in one of the other window display spaces than the window display space where the launcher application is displayed, in response to the new application run command.

Display device and method of controlling the same

An antenna device includes: a feeding rod unit connected to a feeding unit, in which a radio signal is applied to be sent and received to the feeding unit; an end rod unit, disposed at the end of the antenna device, and spaced apart from the feeding rod unit; at least one intermediate rod unit, interposed between the feeding rod unit and the end rod unit; a first helical unit, interposed between the feeding rod unit and the at least one intermediate rod unit; and a second helical unit, interposed between the intermediate rod unit and the end rod unit.

Antenna device

The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second position on the memory module, different from the first position. The second connector is configured to carry high-speed signals for at least one of the memory devices. The high-speed signals are a higher speed form of signaling than the low-speed signals. The memory system may include at least one slot electrically connected to a chip set and at least one memory module electrically connected to the slot via the first connector. A transmission line such as a fiber optic cable electrically connects the second connector and the chip set.

Memory module, method and memory system having the memory module

Example embodiments relate to a receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient in an initial setting mode and may adjust the received data signal based on the determined offset value and equalization coefficient.

Receiving apparatus and method thereof

An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a second differential input signal. The first and second output loads are coupled between a first power supply voltage and the first and second input transistors, respectively, wherein an output terminal is coupled to a node where the first output load is coupled to the first input transistor. The current source is coupled between the first current electrodes of the first and second input transistors and a second power supply voltage, wherein the second output load has an impedance value substantially one half of an impedance value of the first output load. Therefore, a differential output signal may be outputted through a single output terminal.

Pseudo differential output buffer, memory chip and memory system

A semiconductor memory device that may include output drivers, each of which varies a data swing width in response to a correction code, and one or more data swing width control portions. Each of the data swing width control portions may correspond to an output driver, may vary the correction code according to a data swing width of the corresponding output driver to change the data swing width to a correction swing width, and then varies the correction code again to the extent that data of the corresponding output driver are normally transmitted, which may reduce the data swing width.

Semiconductor memory device, memory system having the same, and swing width control method thereof

In an improved construction of a memory device, the memory device includes a first group of pins via which a command/address signals are received and via which data signals are received, and a second group of pins via which the command/address signals are received and via which data signals are output. When the data signals are input to the first group of pins, the command/address signals are received via the second group of pins. When the data signals are output from the second group of pins, the command/address signals are received via the first group of pins.

Configuration of memory device

An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The reference data is delayed from the input data by a delay time shorter than one bit period. The selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of any one of the input data and the reference data in response to the selection signal.

Output driver and output driving method for enhancing initial output data using timing

Provided are a simultaneous bi-directional (SBD) buffer including a self-test circuit having a function of generating an input signal. By using the self-test circuit, self-testing can be accurately performed by generating the input signal in a self-test mode, and a self-test method used by the SBD buffer. The SBD buffer includes an output driver, an input receiver, a first multiplexer, and an input signal generating circuit. The output driver receives an output data signal and outputs the received output data signal to an input/output node. The input receiver receives a signal generated by combining an input data signal inputted to the input/output node with the output data signal, compares the voltage level of the signal with a reference voltage, and outputs the comparison result. The first multiplexer outputs the reference voltage in response to a reference voltage selection signal. The input signal generating circuit generates an input signal used for testing in a test mode and outputs the input signal used for testing as the input data signal. Thus, it is possible to accurately test the performance of the SBD buffer when the SBD buffer performs a self-test.

Simultaneous bi-directional buffer including self-test circuit having function of generating input signal and self testing method of the simultaneous bi-directional buffer

Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to a first input signal, and the second signal response unit responds to a second input signal. The current source unit has a plurality of bias unit pairs for restricting currents provided to the first and second signal response units to respective source currents thereof. The bias unit pairs each include at least two bias units, which are separately arranged on opposite sides of a predetermined imaginary centerline. According to the layout structure of the signal driver of the present invention, there is a benefit in that current mismatch occurring between the first and second current response units is reduced, thus consequently improving the operating characteristics of the signal driver.

Layout structure of signal driver

The open-drain type output buffer includes a first driver and at least one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and does not pull the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the first state when it has been determined that at least two consecutive high voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated.

Open drain type output buffer

A semiconductor memory device and a method for writing and reading data to and from the same comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a predetermined number of write line pairs, a predetermined number of read line pairs, a plurality of write column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of write line pair during a write operation, and a plurality of read column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of read line pairs during a read operation. Accordingly, it is possible to input and output data simultaneously through data input pads and data output pads.

Growing community of inventors

Suwon-si, South Korea

Jung-hwan Choi