Samsung Electronics Co., Ltd.

Rohm and Haas Electronic Materials Korea Ltd.

Samsung Sdi Co., Inc.

Jung-Hwa Lee

Dae-Hwan Kim

Soo-Bong Chang

Jeong-hoon Kook

Jung-suk Kim

Ji-Young Kim

Jae-young Lee

Hyun-ki Kim

Geun Huh

Yeonok Kim

Hong-Jun Lee

Ju-Young Jung

Soon-Hong Ahn

Kyu-Chan Lee

Jun-hyung Kim

Ji-hyun Lee

Chi-wook Kim

Seung-Moon Yoo

Byong-mo Moon

In-Chul Jeong

Seung-Jib Choi

Ju-Ho Jung

Jin-man Han

Dong-il Seo

Sang-Pyo Hong

Chan-yong Lee

Jee-Hyun Ryu

Jong Han Yang

Soo-Young Heo

Bong-Jin Kang

Si-Woo Lee

Whee-Jin Kwon

Lee-June Kim

Dong-Myung Eun

Seung-Min Oh

The present invention relates to a positive-type photosensitive resin composition and a cured film prepared therefrom. The positive-type photosensitive resin composition comprises an acrylic copolymer having a dissolution rate to a developer in a specific range and a compound containing a phenolic hydroxyl group, so that it is possible to attain a high contrast and a high sensitivity pattern when a cured film is formed. Further, it is possible to further enhance the adhesiveness of a pattern when a half-tone, as well as a full-tone, is formed.

Positive-type photosensitive resin composition and cured film prepared therefrom

The present invention relates to a positive-type photosensitive resin composition and a cured film prepared therefrom. The positive-type photosensitive resin composition comprises an acrylic resin and a siloxane copolymer containing a sulfonated diazoquinone group at the terminal thereof. Thus, the film retention rate and adhesiveness can be further enhanced, while the sensitivity is maintained.

A photosensitive resin composition includes (A) an acrylic-based binder resin including a repeating unit represented by Chemical Formula 1, wherein in Chemical Formula 1, each substituent is the same as defined in the detailed description; (B) a cardo-based binder resin including a repeating unit represented by Chemical Formula 2-1 and a repeating unit represented by Chemical Formula 2-2, wherein in Chemical Formula 2-1 and 2-2, each substituent is the same as defined in the detailed description; (C) reactive unsaturated compound; (D) an initiator; (E) a colorant; and (F) a solvent. A photosensitive resin film using the same and a color filter is also provided. 

Photosensitive resin composition, photosensitive resin film using the same and color filter

A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.

Semiconductor memory device comprising sensing circuits with adjacent column selectors

A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving the first word lines; a second driver region at another side of the memory block in the first direction driving the second word lines; a sensing region at a side of the memory block in the second direction controlling the bit lines responsive to signals from drive lines; a first conjunction region at an intersection of the first driver and sensing regions including a first driver driving the drive lines responsive to signals from control lines; and a second conjunction region at an intersection of the second driver and sensing regions, including a second driver driving the drive lines responsive to signals from the control lines.

Semiconductor memory device

Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.

Semiconductor memory device having capacitor for peripheral circuit

A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second transistor has a gate electrode electrically connected to the complementary bit line and a first electrode electrically connected to the bit line. An equalizing transistor is disposed between the gate electrode of the first transistor and the gate electrode of the second transistor. The first electrode of the first transistor and a first electrode of the equalizing transistor are electrically connected to each other, and the first electrode of the second transistor and a second electrode of the equalizing transistor are electrically connected to each other.

Sense amplifiers and semiconductor devices including the same

A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.

Semiconductor device having decoupling capacitor and method of fabricating the same

A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column selection circuit including a first column selection transistor and a second column selection transistor, wherein the first and the second selection transistors share a drain and electrically couple the complementary bit line pair to a complementary local input/output line pair, respectively. As a result, the data error due to the distance mismatching can be reduced.

Memory core with single contacts and semiconductor memory device having the same

A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

High voltage generating circuit preserving charge pumping efficiency

A high voltage generator is provided. The high voltage generator may comprise a high voltage output node, a plurality of pumping stages, a plurality of charge transfer elements, and a field relieving unit. The plurality of pumping stages sequentially pump charges in response to a sequentially enabled plurality of pump signals and output the pumped charges, respectively. The plurality of charge transfer elements sequentially transfer the charges sequentially pumped by the plurality of pumping stages to the next pumping stage and transfer the charge of an output node of the last pumping stage to the high voltage output node. The field relieving unit reduces the voltage of the input terminal of at least one of the plurality of charge transfer elements. The high voltage generator reduces hot carrier injection in charge transfer transistors without decreasing pumping efficiency.

High voltage generator

A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage generators configured to generate a boosted voltage having different current driving capabilities to activate the non-edge sub-arrays and the edge sub-arrays and to supply the boosted voltage to the memory cell array.

Circuit and method of generating a boosted voltage in a semiconductor memory device

Provided is a bit line bridge detection method for selectively floating even-numbered or odd-numbered bit lines. The bit line bridge detection method simultaneously activates even-numbered sense amplifiers and odd-numbered sense amplifiers in response to a sense amplifier enable signal. The even-numbered sense amplifiers and the odd-numbered sense amplifiers are selectively disabled in response to a sense amplifier disable signal generated at a predetermined time after the sense amplifier enable signal is generated, and an even-numbered or odd-numbered sense amplifier selection signal which is stored in a mode register. As a result, the even-numbered bit lines and the odd-numbered bit lines are selectively floated. If data input to memory cells is inverted, a bit line bridge is detected.

Growing community of inventors

Suwon-si, South Korea

Jung-Hwa Lee