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Inotera Memories, Inc.

Jung-Hung Wang

Shin Bin Huang

Chung-Yi Chang

Ming-Hwa Tai

A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.

Method for manufacturing capacitor lower electrodes of semiconductor memory

A rechargeable battery assembly including a charging circuit and an electric plug assembly for connecting external power supply to the charging circuit, the charging circuit including an AC power input means to receive AC power supply, voltage dropping and power supply rectifying means connected to the AC power input means to drop AC power supply voltage and to change AC power supply into DC power supply, a battery, voltage detection and power supply control means, switch means connected between the voltage dropping and power supply rectifying means and controlled by the voltage detection and power supply control means to charge the battery.

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Taipei, Taiwan

Jung-Hung Wang