National Science Council

National Kaohsiung Normal University

National Science Council of Republic of China

National Science Counsel of Republic of China

Jung-Hui Tsai

Wen-Chau Liu

Wen-Shiung Lour

Kun-Wei Lin

Kuo-Hui Yu

Wen-Lung Chang

New pseudomorphic high electron mobility transistors (pHEMT's) with extremely high device linearity having an n/p/n camel-gate heterostructure and &#x3b4;-doped sheet structure is disclosed. For the example of InGaP/InGaAs/GaAs &#x3b4;-doped pHEMT's with an n-GaAs/p-InGaP/n-InGaP camel-gate structure, due to the p-n depletion from p-InGaP gate to channel region and the presence of large conduction band discontinuity (&#x394;Ec) at InGaP/InGaAs heterostructure, the turn-on voltage of gate is larger than 1.7 V. Attributed to the applied gate voltage partly lying on the camel gate and influence of the carrier modulation, the change of total depletion thickness under gate bias is relatively small, and high drain current and linear transconductance can be achieved, simultaneously. The excellent device performances provide a promise for linear and large signal amplifiers and high-frequency circuit applications.

Pseudomorphic high electron mobility field effect transistor with high device linearity

Novel heterojunction bipolar transistors (HBT's) with high current gain and extremely low offset voltage are disclosed. Owing to the insertion of spacer/&dgr;-doped sheet/spacer at base-emitter (B-E) heterojunction in this invention, the potential spike at B-E junction can be eliminated and the confinement effect for holes are enhanced. The potential spike is not observed under large B-E bias, and the offset voltage is still relatively small with small increase. In particular, for the HBT's with large conduction band discontinuity, the method of the invention is more efficient for completely eliminating the potential spike. For the example of InP/GaInAs HBT, a maximum common-emitter current gain of 455 and above 320 at I &equals;5 &mgr;A, and a low offset voltage less 60 mV are achieved.

Heterojunction bipolar transistors with extremely low offset voltage and high current gain

The invention relates to a high-breakdown voltage heterostructure field-effect transistor (FET), which can be used under a high temperature condition. The FET device from bottom upward in succession includes a semiconductor substrate, a buffer layer, a delta-doped sheet, an undoped layer, a sub-channel layer, an active channel layer, a gate layer, and an ohmic contact layer.

High-breakdown voltage heterostructure field-effect transistor for high temperature operations

The present provides two low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistors which include AlInAs heterostructure-confinement and AlInAs/GaInAs superlattice-confinement bipolar transistors. In the present invention, an n GaInAs emitter layer is inserted at AlGaAs confinement layer/GaInAs base layer to reduce offset voltage and potential spike at an E-B junction.

Low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar

The invention relates to the structure of the camel-gate field-effect transistor with multiple modulation-doped channels. The device structure, from the bottom to the top in succession, includes the substrate, the buffer layer, the multiple modulation-doped channels, the thin and complete depletion layer, and the ohmic contact layer. The transistor is characterized by a camel-gate diode, which is composed of the multiple modulation-doped channels, the thin and complete depletion layer and the ohmic contact layer. The gate structure may achieve the high potential height between the gate electrode and the source electrode as well as the high breakdown voltage performance. Furthermore, the use of multiple modulation-doped channels, made of n-type GaAs materials with different thickness and doped concentration, can exhibit excellent properties of high output current, large and linear transconductances.

Camel-gate field-effect transistor with multiple modulation-doped

The invention presents a structure of heterostructure-emitter and heterostructure-base transistor. The device structure are, from bottom upward in succession, a substrate, a buffer layer, a collector layer, a base layer, a quantum well, an emitter layer, a confinement layer and an ohmic contact layer. Of them, except the quantum well which is made of InGaAs and the confinement layer which is formed by AlGaAs, the rest are all made of GaAs material. Base on the design of the heterostructure of base and emitter, a transistor of such structure, under normal operation mode, possesses high current gain and low offset voltage so as to reduce undesirable power consumption. In addition, under the inverted operation mode, the interesting multiple S-shaped negative-differential-resistance may be obtained due to the avalanche multiplication and two-stage carrier confinement effects. These properties cause the device of the invention to provide good promise for amplification, oscillator, and multiple-valued logic circuits applications.

Growing community of inventors

Kaohsiung, Taiwan

Jung-Hui Tsai