Taiwan Semiconductor Manufacturing Comp. Ltd.

Jung-Hui Kao

Kong-Beng Thei

Bao-Ru Young

Huan-Just Lin

Pei-Ren Jeng

Chih-Tang Peng

Jin-Aun Ng

Jen-Sheng Yang

Ta-Wei Lin

Yuan-Tien Tu

Chih-Yang Yeh

Hui-Wen Lin

Shih-Hao Lo

Maxi Chang

Harry-Hak-Lay Chuang

Harry Chuang

Sheng-Chen Chung

Yi-Huan Chen

Fu-Jier Fan

Yi-Sheng Chen

Chung Long Cheng

Kong-beng Thei

Kau-Chu Lin

Jing-Jung Huang

Mong-Song Liang

Wen-Huei Guo

Mong Song Liang

Chung-Long Cheng

Chun Chieh Chang

Kuo-Fong Chen

Ching En Chen

Ryan Chia-Jen Chen

Jen-Yuan Chang

Gwan Sin Chang

Hak-Lay Chuang

Shun-Jang Liao

Fu-Hsiung Yang

Gary Shen

Chih-Tsung Yao

A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.

Method of manufacturing a semiconductor device

A method includes forming an integrated circuit and a testing pattern over a die region of a wafer and a scribe line region of the wafer, respectively, in which the integrated circuit and the testing pattern are formed by a same fabrication process; connecting a via of a testing chip to a testing pad of the testing pattern; performing a testing process to the die region by detecting electrical properties of the testing pattern through the testing chip; after the testing process is completed, forming an interconnection structure over the integrated circuit, in which the interconnection structure includes conductive features electrically connected to the integrated circuit; and after the interconnection structure is formed over the integrated circuit performing an singulation process through the scribe line region of the wafer, such that the die region of the wafer is singulated into an individual die.

Method of forming testing module and method for using the same

A plurality of devices for testing, connected in series using one or more redistribution layers (RDLs), are used to perform a semiconductor device test on a plurality of dies. As a result, the semiconductor device test may support thousands of gross dies per wafer or greater (e.g., 10,000 dies or greater). Furthermore, the RDL(s) may be removed after use. In some implementations, the devices for testing corresponding to the dies may execute the semiconductor device test sequentially. Accordingly, test data may be generated and may include a bit sequence, where a first bit in the bit sequence indicates an overall outcome for the test and one or more subsequent bits in the bit sequence indicate respective outcomes for each semiconductor dies or for each line of the semiconductor device test.

Semiconductor testing device and method of operating the same

A semiconductor structure includes a substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region; a first isolation disposed in the first region, wherein the first isolation is between a first source and a first drain, a first spacer overlaps the first isolation, the first isolation is separated from the first spacer by a first gate dielectric.

Semiconductor structure

A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.

Semiconductor device

A semiconductor structure includes a semiconductor substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region, wherein a voltage level of the first device is greater than a voltage level of the second device; a first isolation disposed in the first region, wherein the first isolation includes a first depth; and a second isolation disposed in the second region, wherein the second isolation includes a second depth, and the first depth is greater than the second depth.

A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Self-aligned insulated film for high-K metal gate device

An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Self-aligned insulated film for high-k metal gate device

An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.

A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.

A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

3-dimensional device design layout

A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

Contact scheme for MOSFETs

A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

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Hsin-Chu, Taiwan

Jung-Hui Kao