Taiwan Semiconductor Manufacturing Comp. Ltd.

Jung-Hsuan Chen

Yen-Huei Chen

Hung-Jen Liao

Li-Chun Tien

Shao-Yu Chou

You-Cheng Xiao

Ting-Wei Chiang

Hong-Chen Cheng

Sahil Preet Singh

Avinash Chander

Albert Ying

Kao-Cheng Lin

Cheng Hung Lee

Pin-Dai Sue

Ru-Yu Wang

Chien Chi Tien

Jhih-Siang Hu

Chien Chi Linus Tien

Chung-Hsing Wang

Kuo-Hua Pan

Ching-Wei Wu

Chiting Cheng

Jui-Che Tsai

Hsien-Yu Pan

Ming-Yi Lee

Ze-Sian Lu

Hui-Wen Li

Chung-Ji Lu

Hsin-Hsin Ko

Tzung-Yo Hung

May Chang

Shu Cheng Huang

A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

Semiconductor device

A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.

Semiconductor device with increased unity density

A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

Method of forming semiconductor device with increased unit density

A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.

A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.

Semiconductor device including memory cell and fin arrangements

A sense amplifier (SA) includes a semiconductor substrate having a source/drain (S/D) diffusion region; a pair of SA sensing devices both disposed in the S/D diffusion region; an SA enabling device disposed in the same S/D diffusion region as where the pair of SA sensing devices are disposed in; and a sense amplifier enabling signal (SAE) line for carrying an SAE signal, for turning on the SA enabling device to discharge one of the pair of SA sensing devices during a data read from the sense amplifier, wherein the SA enabling device is arranged to provide buffer protection for source/drain terminals of the pair of SA sensing devices.

Sense amplifier layout for FinFET technology

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.

A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Layout scheme and method for forming device cells in semiconductor devices

Growing community of inventors

Hsinchu, Taiwan

Jung-Hsuan Chen