Magnachip Semiconductor, Inc.

Haechitech Corporation

Jung Hoon Sul

Dong Il Seo

Brandon Kwon

Jae Won Kim

Sang Kyung Kim

Dae Young Yoo

Duk Min Lee

Jin Seok Yang

Myung Woo Lee

Seung Ryeol Lee

Tak Jun Oh

A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

Slew rate adjusting circuit for adjusting slew rate, buffer circuit including same, and slew rate adjusting method

A multi-vision display device includes a timing controller, a plurality of display panels, and a plurality of display driver integrated circuits (ICs). The timing controller is configured to receive source data and timing signals from a host, and generate a data packet comprising image data and control data. The plurality of display driver ICs each is connected to any one of the plurality of display panels. The control data includes a panel identifier indicating a number of display panels of the plurality of display panels connected to the display driver IC prior to a corresponding display panel connected to the display driver IC. Adjacent ones of the plurality of display driver ICs are connected to each other, modulate the panel identifier provided from one among the timing controller and a front end display driver IC, and provide the modulated panel identifier to a rear end display driver IC.

Cascaded display driver IC and multi-vision display device including the same

A device for driving a display panel includes a display driving integrated circuit (IC) configured to transmit image data to the display panel, a display control IC configured to receive compressed image data from a host and including a timing controller configured to control the display driving IC, and a non-volatile memory configured to transmit data to and receive data from the display control IC, and configured to store driving parameters necessary for operation of the display driving IC.

Chip solution device for driving display panel comprising display driving integrated circuit (IC) and display control IC

A capacitor type humidity sensor is provided, where a reference capacitor (C) is provided as an MIM (metal insulator metal) capacitor or a PIP (polysilicon insulator polysilicon) capacitor. The MIM capacitor or PIP capacitor is aligned in array structure to enable the trimming. The capacitor type humidity sensor includes a sensing capacitor (C) connected between negative (&#x2212;) drive voltage terminal (&#x2212;V) and an inverting terminal (&#x2212;) of an operational amplifier, and a reference capacitor (C) connected between positive (+) drive voltage terminal (+V) and an output node (a) of the sensing capacitor (C), wherein the sensing capacitor (C) is configured to trim the reference capacitor (C).

Capacitor type humidity sensor

A Complementary Metal-Oxide-Semiconductor (CMOS) analog switch has a circuit structure such that when a supply voltage is applied, the CMOS analog switch biases voltages at both ends of a Metal-Oxide-Semiconductor Field Effect Transistor (MOS) device, which switches on upon application of supply voltage, to a substrate node of MOS, or biases the substrate voltage of MOS device to a ground voltage state during a switching-off operation. The substrate voltage of MOS device in floating state is still biased to the ground voltage state even when abnormal, high voltages are applied to both ends of the MOS device. As a result, threshold voltage and conduction resistance decrease compared to related analog switches, and frequency bandwidth increases.

Complementary metal-oxide-semiconductor (CMOS) analog switch circuit

There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters.

Growing community of inventors

Seoul, South Korea

Jung Hoon Sul