Samsung Electronics Co., Ltd.

Jung-hoon Park

Kohji Kanamori

Young-Woo Park

Sung-Ho Eun

Shin-Hwan Kang

Seul-ji Song

Seung-Jae Lee

Sang-Wan Nam

Chi-Weon Yoon

Sung-won Yun

Kyung-Hwa Kang

A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.

Semiconductor memory device

A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

Methods of manufacturing vertical memory devices

Vertical memory devices and methods of manufacturing the same

A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

Nonvolatile memory device with 3D memory cell array

A non-volatile semiconductor memory device and method of programming the non-volatile semiconductor memory device are disclosed. The non-volatile semiconductor memory device includes a selected word-line and unselected word-lines including at least one unselected word-line to which a first voltage signal is applied. The selected word-line is coupled to a selected memory transistor and receives a program voltage signal in response to a program voltage enable signal. A first voltage signal is applied to the at least one unselected word-line. The first voltage signal has a voltage level of a reduced pass voltage signal before the program voltage enable signal is activated and has a voltage level of a pass voltage signal while the program voltage enable signal is activated.

Non-volatile memory devices and methods of programming the same

A flash memory device includes a core region, high-voltage pump regions disposed at one side of the core region, and a peripheral control region disposed at one side of the core region and between the high-voltage pump regions.

Layout structure for use in flash memory device

A NAND flash memory device which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.

Growing community of inventors

Yongin-si, South Korea

Jung-hoon Park