Electronics and Telecommunications Research Institute

Samsung Electronics Co., Ltd.

Sk Chemicals Co., Ltd.

Kt Corporation

Sk Telecom Company, Ltd.

Hanaro Telecom., Inc.

Jung-Hoon Oh

Jae-Sun Kim

Bong-Yong Lee

Keun-Ho Ryu

Young-Hoon Kim

Gweon-Do Jo

Ye-Ji Jeon

Sooheun Lee

Soo-Min Lee

Jae-Ho Jung

Young-il Kim

Joon-Hyung Kim

Seung-yong Lee

Hyun-Uk Hwang

Jun-Su Kim

Joong-Soo Han

Hyun-Kyu Chung

Hyun Jung Lee

Yong-Su Lee

Kwang-Chun Lee

Ju Young Lee

Hyun-jae Kim

Hun-Taek Kim

Sung-hoon Park

Jung Bum Yi

Byeong-Hwan Cho

Won-Ho Kim

Sang-hwan Kang

Ki-Bom Kim

Yong-Hyuk Kim

Byung-Wook Park

Hoe-chul Jung

Key-An Um

Jeong-yang Kim

Young-Soon Lim

Jung-Mu Lee

Hye-Jin Jeong

Disclosed herein are a logical imaging apparatus and method for digital forensic triage. The logical imaging method for digital forensic triage includes receiving files selected as a digital evidence target, creating a logical imaging file, inside of which is formatted in a predetermined file system structure, recording the selected files in accordance with the file system structure of the created logical imaging file, and storing selected file list information about a list of the recorded selected files, and creating a separate selected list information file and a separate logical imaging summary file outside the logical imaging file.

Logical imaging apparatus and method for digital forensic triage

Disclosed herein are an evidence collection guidance method and apparatus for file selection. The evidence collection guidance method includes generating pieces of preliminary analysis information that are pieces of collection target information, setting levels of the pieces of preliminary analysis information based on predefined rules, and generating and outputting notification information including summary description information and follow-up measure items related to the pieces of preliminary analysis information corresponding to the levels.

Evidence collection guidance method and apparatus for file selection and computer-readable storage medium

Disclosed is a composition effective in reducing skin wrinkles. The composition comprises a phosphodiesterase 5 (PDE5) inhibitor, preferably the compound of chemical formula 1, more preferably, mirodenafil as an active ingredient. Further disclosed is a method for reducing skin wrinkles using the composition.

Composition for reducing skin wrinkles including PDE5 inhibitor

Disclosed is a composition effective in reducing skin wrinkles. The composition comprises or uses a phosphodiesterase 5 (PDE5) inhibitor as an active ingredient. Further disclosed is a method for reducing skin wrinkles using the composition.

A digital pre-distortion (DPD) power amplifying apparatus and a method for digitally controlling synchronization of the DPD power amplifying apparatus, which includes a power amplifier, a bias shifter and a DPD unit, are provided. The method includes acquiring a DPD path delay time at a path along which an input signal is fed back to the DPD unit; delaying an input signal incoming to the power amplifier by the DPD path delay time and acquiring synchronization by delaying a bias signal a predetermined number of times until the bias signal and the delayed input signal are synchronized with each other; and in response to synchronization between the bias signal and the delayed input signal being established, pre-distorting the input signal according to a feedback signal output from the power amplifier.

Digital pre-distortion power amplifying apparatus and method for digitally controlling synchronization thereof

A distortion compensation apparatus and an apparatus and method for transmitting a signal are provided. The distortion compensation apparatus can extract precise distortion information by adding an additional signal to an input signal during the compensation of distortion in a nonlinear apparatus, and can linearize the nonlinear properties of the nonlinear apparatus using the distortion information. The apparatus for transmitting a signal can output a signal linearized by the same method as that used by the distortion compensation apparatus.

Distortion compensation apparatus and apparatus and method for transmitting signal

2-pyridyl substituted imidazoles of the formula (I) as shown in claim, are provided, which are useful in the treatment of diseases mediated by ALK5 or ALK4 inhibitors or both.

2-pyridyl substituted imidazoles as ALK5 and/or ALK4 inhibitors

Provided are a method of controlling power of an access uplink using a relay station (RS) and a system thereof. When a base station (BS) decides that the subject of power control of the access uplink is itself, the BS generates a message for power control of the access uplink based on channel quality measurement information reported from the RS and transmits the power control message to a subscriber station (SS), and when the BS decides that the subject of power control of the access uplink is the RS, the RS generates a message for power control of the access uplink based on channel quality measurement information and transmits the power control message to the SS. Thus, fast power control of the access uplink can be performed.

Method of controlling power of access uplink using relay station and system thereof

A pre-distortion apparatus of a power amplifier includes: a pre-distortion unit configured to generate a pre-distorted signal of an input signal by calculating a magnitude of the input signal and outputting a complex correction coefficient corresponding to the calculated magnitude of the input signal, and provide the generated pre-distorted signal as an input of the power amplifier; and a complex correct coefficient update unit configured to generate an error signal by comparing an output signal of the power amplifier with the input signal and updating the complex correction coefficient to minimize a magnitude of the generated error signal, wherein the pre-distortion unit provides a constant bias value corresponding to the magnitude of the input signal as a bias of the power amplifier while updating the complex correction coefficient.

Pre-distortion apparatus of power amplifier and method thereof

In a communication system, subchannel state information for a plurality of user equipments (UEs) are collected, and a plurality of subchannel state prediction parameter values for the respective UEs are calculated using the subchannel state information. In addition, the communication system allocates at least one subchannel among the plurality of subchannels to a first UE having the highest priority. Subsequently, the communication system determines whether to allocate additional power to the at least one subchannel based on the plurality of subchannel state prediction parameter values, and allocates additional power to a subchannel that needs the additional power among the at least one subchannel.

Apparatus and method for allocating subchannel and power in communication system, and transmitting apparatus

A fast locking phase locked loop includes a first phase frequency detector (PFD), a second PFD, a lock detector, an up-signal output unit, a down-signal output unit, a selective charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The first PFD outputs a first up-signal and a first down-signal. The second PFD outputs a second up-signal and a second down-signal. The lock detector outputs an inverted lock signal. The selective charge pump outputs a pumping current. The loop filter generates a control voltage in response to the pumping current. The VCO generates the external clock signal having a frequency determined in accordance with the control voltage. The PLL has a faster locking time because the PFDs included in the PLL are capable of detecting a phase difference in a missing edge.

Fast locking phase locked loop for synchronization with an input signal

A phase locked loop (PLL) circuit having a deadlock protection circuit and a deadlock protection method of the PLL circuit are provided. The PLL circuit includes: a phase frequency detector, which receives an input clock signal and a divided clock signal and compares the phase and frequency of the input clock signal with the phase and frequency of the divided clock signal; a charge pump, which receives an output signal of the phase frequency detector; a voltage-controlled oscillator, which oscillates in response to an output voltage of the charge pump; a main divider, which divides the frequency of an first output clock signal of the voltage-controlled oscillator and outputs the divided clock signal as the division result; and a deadlock protection circuit, which is electrically coupled to an output port of the voltage-controlled oscillator and an input port of the main divider, and divides the frequency of the first output clock signal of the voltage-controlled oscillator and then provides the division result to the main divider if the frequency of the first output clock signal of the voltage-controlled oscillator is above a threshold frequency.

Phase locked loop circuit having deadlock protection circuit and methods of operating same

The socket assembly includes a guide block, a guide part and a pressurizing plate. The guide block is in a terminal region of a test board, the guide block defining an area into which an integrated circuit can be inserted opposite terminals formed on the test board in the terminal region. The guide part is provided on an inner side wall of the guide block, to guide an insertion position of the integrated circuit so that respective leads of the integrated circuit are aligned with the corresponding terminals of the test board. The pressurizing plate is adapted to interface with the guide block, the pressurizing plate including a pressurizing protrusion on a surface thereof, such that when the pressurizing plate is applied to the guide block, the respective leads of the integrated circuit are urged to connect with the corresponding terminals of the test board.

Socket assembly for test of integrated circuit, and its integrated circuit and tester

A tester and method for testing linearity of an analog to digital converter without being influenced by noise, includes a controller that outputs a sampling frequency clock to convert an analog signal into a digital signal, that digitally filters the digitized code value, that generates a histogram responsive to the filtered digitized code value according to a predetermined program, and that controls display of the histogram; a signal generator that generates ground voltage and a triangular wave signal; an analog to digital converter that converts the analog triangular wave signal generated by the signal generator into a digital signal and that outputs the digital signal; a memory that stores the digitized code value converted by the analog to digital converter under control of the controller; and a display that displays the histogram related to the digitally filtered code value generated under control of the controller.

Apparatus and method for testing linearity of an analog to digital converter

Growing community of inventors

Seoul, South Korea

Jung-Hoon Oh