Samsung Electronics Co., Ltd.

Jung-Ho Song

Sang-gu Kang

Hee-Won Lee

Minsu Kim

Il Han Park

Su Chang Jeon

Ji-Suk Kim

Ju-Seok Lee

Seung-Jae Lee

Jin-Yub Lee

Il-Han Park

Sang-Won Hwang

Ilhan Park

Ju Seok Lee

Jae-Woo Im

Min-Seop Jeong

Su-Yong Kim

Yang-Lo Ahn

Nam Hee Lee

Ki-won Lee

Dong-il Han

Ho Joon Kim

Sang-So Park

A semiconductor device includes a memory cell array including a plurality of memory blocks, a control logic, a level shifter configured to generate a first internal voltage and a second internal voltage lower than the first internal voltage using a received external voltage on the basis of a control signal from the control logic, and a row decoder configured to provide the first and second internal voltages generated by the level shifter to the memory cell array. The level shifter generates the first internal voltage using the external voltage, generates the second internal voltage using the generated first internal voltage in a power-up mode of the semiconductor device, and generates the second internal voltage using the external voltage in a standby mode of the semiconductor device.

Level shifter and level shifting method and semiconductor device including the same

An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

Nonvolatile memory device and operating method thereof

A program verification method is for a nonvolatile memory device which programs a plurality of memory cells. The program verification method includes applying a plurality of verification voltages, and determining whether programming of memory cells, having different target threshold voltage distributions, from among the plurality of memory cells is completed based on one of the plurality of verification voltages.

Nonvolatile memory devices and program verification methods using one verification voltage to verify memory cells having different target states

A method of programming a nonvolatile memory device is provided which includes applying a program voltage to selected ones of a plurality of memory cells; applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied; sensing the memory cells to which the selected verification voltage is applied; selecting memory cells programmed to a target state referring to the sensing result and target state data; and determining whether programming of the selected memory cells is passed or failed.

To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Methods of programming multi-level cell nonvolatile memory devices and devices so operating

A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.

Nonvolatile memory device and method of reading data in nonvolatile memory device

A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

Non-volatile memory device

A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.

Systems and methods for performing a program-verify process on a nonvolatile memory by selectively pre-charging bit lines associated with memory cells during the verify operations

A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.

Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same

A system for accessing a node of a private network includes an assigning portion for assigning external port values to respective network nodes based on information collected from the network nodes of the private network, and storing the assigned external port values; an exchanging portion for exchanging the external port values of the respective network nodes of private networks; and an address converting portion for converting the external port values into corresponding private IP addresses and internal port values when a network node of one private network accesses another network node of another private network by using the external port values of another network node of another private network. Accordingly, a network node of a private network without a global IP address becomes accessible.

System and method for accessing node of private network

A method of generating an IEEE 1394 virtual network in which a virtual network is constructed on the IEEE 1394 network and respective nodes sense the virtual network and a controller for generating the virtual network. The method steps of connecting a virtual network controller for generating a virtual self ID packet including a virtual node ID information required for constructing a virtual network to a predetermined IEEE 1394 network, the respective nodes and the virtual network controller constructing the IEEE 1394 network for determining whether they are branches or leaves by performing virtual bus initialization, determining parent ports and child ports with respect to the ports of the respective nodes and a root node by performing a virtual tree identification, and determining the physical node IDs of the respective nodes by sending the prepared virtual self ID packet.

Growing community of inventors

Suwon-si, South Korea

Jung-Ho Song