Samsung Electronics Co., Ltd.

Gangneung-wonju National University Industry Academy Cooperation Group

Gangneung-wongju National University Industrial Academy Cooperation Group

Jung-Ho Moon

Chul-soon Kwon

Jae-Hyun Park

Jeong-Uk Han

Hee-Seog Jeon

Jae-Min Yu

Yong-Sun Lee

In-Gu Yoon

Don-Woo Lee

Han-Su Chung

Young-Ho Kim

Tae-yun Chung

Yong-Kyu Lee

Yong-kyu Lee

Myung-Jo Chun

Soung-Youb Ha

In-gu Yoon

Sung-Wook Park

Yong-Tae Kim

Seung-Jin Yang

Young-cheon Jeong

Jae-won Um

Lae-Jeong Park

Jae-min Yu

Jung-Hun Cho

Tae Yun Chung

Hyuck-Soo Yang

Eung-yung Ahn

Sung-Yung Jeon

Provided is a terminal node device including: a communication module communicating with an external sink node device and another terminal node device; sensor modules; and a control unit allowing the terminal node device to be operated while allowing the terminal node device to transition into one of the initial, synchronous, and leave states. In the initial state, the control unit scans a received message; if a beacon message is received from a sink node device, the control unit transitions into the synchronous state; and if not for a predetermined time, the control unit transitions into the leave state. Accordingly, if a beacon message is received from the sink node device, the terminal node device transitions into the synchronous state to constitute a server-based wireless sensor network; and if not, the terminal node device transitions into the leave state to constitute an independent sensor network.

Terminal node device and wireless sensor network system using the terminal node device

A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.

Mask read-only memory having a fake select transistor

Provided are a double linked wireless sensor network capable of performing bidirectional communication and a method of transmitting and receiving data. In each of nodes constituting the wireless sensor network, an active duration and an inactive duration are alternately repeated, and the active duration is configured to include an upstream duration, an intermission duration, and a downstream duration. Each of the downstream duration and the upstream duration is configured to sequentially include a second receive slot, a second receive processing slot, a first receive slot, a first receive processing slot, a transmit slot, a transmit processing slot, a first acknowledge slot, a first acknowledge processing slot, a second acknowledge slot, and a second acknowledge processing slot, and wherein bidirectional communication can be performed between the sink node and the terminal node in a single period of the active duration. In the wireless sensor network, a transmit processing duration TXP is maintained in a receiving mode capable of receiving data from other nodes, so that a new node can be easily joined as a terminal node or an intermediate node. In addition, in the wireless sensor network, each of the upstream duration and the downstream duration is provided with consecutive two receiving durations, so that, although links to consecutive two nodes are disconnected, it is possible to simply recover the links.

Double linked wireless sensor network being capable of bidirectional communication and method thereof

Disclosed is a wireless sensor network with a linear structure capable of bidirectional communication. The wireless sensor network includes a plurality of nodes linearly connected from a sink node to a terminal node by connecting each node to a single upper-level node and a single lower-level node, each node has an active period for transmitting/receiving data to/from its upper-level node and lower-level node, the active period includes a downstream duration for transmitting data/commands from the sink node to the terminal node and an upstream duration for transmitting data/commands from the terminal node to the sink node, and each of the upstream and downstream durations sequentially includes RX, TX, and ACK intervals, so that bidirectional communication between the sink node and the terminal node can be performed within a single active period.

Wireless sensor network with linear structure being capable of bidirectional communication and method thereof

A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

Mask ROM device, semiconductor device including the mask ROM device, and methods of fabricating mask ROM device and semiconductor device

In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same

A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on the semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be electrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

Nonvolatile memory device and method of fabricating the same

A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

Method of fabricating nonvolatile memory device

A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device

A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

Method of fabricating a flash memory cell

There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

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Seoul, South Korea

Jung-Ho Moon