Agere Systems Inc.

Lsi Corporation

Jung Ho Cho

Lane Allen Smith

Vladimir Sindalovsky

Thaddeus John Gabara

Robert M Kylor

In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.

Alignment for multiple FIFO pointers

The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros adjacent to one another. Moreover, these internal signal paths permit efficient distribution of a common source signal to each of such connected macros. The layout of the internal macro cell signal paths of the present invention also permits each of these macros to be reflected about its Y-axis, thereby increasing its versatility in being utilized in various circuit designs.

Symmetric signal distribution through abutment connection

A latch circuit having reduced propagation delay and set-up and hold times comprises at least one set of cross-coupled transistor devices arranged between an upper supply terminal of the circuit and a lower supply terminal of the circuit. A first input transistor device is coupled in parallel with a first one of the transistor devices of the set of cross-coupled transistor devices, and a second input transistor device is coupled in parallel with a second one of the transistor devices of the set of cross-coupled transistor devices. The first and second input transistor devices are adapted for application of respective uncomplemented and complemented inputs thereto during an initialization mode of the latch circuit. Uncomplemented and complemented output signals are generated at corresponding output terminals associated with the set of cross-coupled transistor devices during an evaluation mode of the latch circuit. The latch circuit may be implemented as a master in a master-slave configuration having additional slave circuitry so as to provide a tradeoff between operating speed and a desired set-up and hold time window.

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Allentown, PA, United States of America

Jung Ho Cho