Hewlett-packard Development Company, L.P.

Samsung Electronics Co., Ltd.

Seoul National University

Snu Rdb Foundation

Wisconsin Alumni Research Foundation

Skhynix Inc.

Leland Stanford Junior University

Nhn Corporation

The Catholic University of Korea Industry-Academic Cooperation Foundation

Hewlett Packard Enterprise Development LP

Jung Ho Ahn

Moray McLaren

Norman Paul Jouppi

Nathan Lorenzo Binkert

Robert S Schreiber

Alan Lynn Davis

Ho-Young Song

Nam Sung Kim

Seung Wook Lee

Chan-Kyung Kim

Sang-Joon Hwang

Young-Hoon Son

Seong-Il O

Hweesoo Kim

Jacob B Leverich

William James Dally

Michael Renne Ty Tan

Jae Hyun Park

Jae Ho Lee

Sang Il Park

Dong Hwan Kim

Dongyoung Kim

Jae Bong Chun

Sunjung Lee

Seung Hwan Kim

Yong Jin Kim

Young Hwan Son

Jaewan Choi

Nam Hoon Kim

Eojin Lee

Bo Ram Namgoong

Norm Jouppi

Al Davis

Seong Il O

Young Hyeon Jang

Jun Beom Lee

Namsung Kim

Sang Ho Choe

Nam Hong Kim

Micheal Jae Min Kim

Mattan Erez

Ingab Kang

Moray Mclaren

Proposed are counter-based selective row hammer refresh apparatus and method for row hammer prevention and, more particularly, proposed are an apparatus and a method for reducing energy consumption of dynamic random access memory (DRAM) by improving counter-based algorithms for solving a row hammer problem when applying a refresh management (RFM) command that is a new command applied to the latest DRAM standards, such as DDR5, LPDDR5, and the like.

Counter-based selective row hammer refresh apparatus and method for row hammer prevention

An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.

Accelerator and electronic device including the same

The present invention relates to a system and method for monitoring the safety of users in a shaded area, wherein location information about an RFID post installed in a shaded area is identified by means of an RFID tag, so that the location of a work group working in the shaded area can be transmitted to a control server in real time, and the control server compares the location of the work group with operation information about trains, thereby determining whether the work group is in danger or not, makes notification the same, so that the safety of the work group can be secured.

Group leader selection method, and user safety monitoring system and method

A neural processor is provided. The neural processor includes a matrix device which is configured to generate an output feature map by processing a standard convolution operation and which has a systolic array architecture, and accelerators with an adder-tree structure which are configured to process depth-wise convolution operations for each of elements of the output feature map corresponding to lanes of the matrix device.

Neural processor

An electronic device according to an embodiment of the present invention comprises a first conductive plate; and a second conductive plate which extends from the first conductive plate at a first angle to the first conductive plate, wherein the first conductive plate and the second conductive plate comprise a conductive member which forms a cavity opened in a first direction perpendicular to the first conductive plate; a first radiation unit which is disposed apart from the first conductive plate by a first distance in a first direction; a second radiation unit which is disposed apart from the first conductive plate by a second distance in a second direction opposite to the first direction; at least one wireless communication circuit which feeds electricity to the first radiation unit and the second radiation unit; and a processor which is electrically connected with the wireless communication circuit, the processor can be set to cause the wireless communication circuit to receive a signal of a first frequency having a directivity in the first direction on the basis of the cavity formed by the first radiation unit and the conductive member, and to receive a second frequency signal on the basis of the coupling of the second radiation unit and at least a portion of the conductive member. In addition, various embodiments understood from the specification may be possible.

Electronic device comprising antenna

A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

Memory module, memory device, and processing device having a processor mode, and memory system

A network server includes a webpage provider, a user monitor, and a content selector. The webpage provider is configured to provide to a user terminal a webpage including a first region and a second region arranged in a first direction in response to a request from the user terminal. The first region includes pieces of first content arranged in a second direction crossing the first direction, and the second region includes pieces of second content arranged in the second direction. The user monitor is configured to detect an action of the user terminal for the pieces of first content. The content selector is configured to search for pieces of third content related to the content for which the action of the user terminal is detected among the pieces of first content in a database, and to include the pieces of third content in the second region.

Network server and method for providing webpage to user terminal

A row hammer prevention circuit for providing a reference address to perform an additional refresh operation includes a history storage circuit configured to store one or more first addresses, each of the first addresses having been provided as the reference address. The row hammer prevention circuit further includes an address storage circuit configured to store a row address corresponding to an active command, a reference address storage circuit configured to store one or more second addresses, and a control circuit configured to provide the reference address in response to a refresh command.

Row hammer prevention circuit, a memory module including the row hammer prevention circuit, and a memory system including the memory module

A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips. The method for the error correction of memory may include reading, by a first ECC engine unit included in each of a plurality of memory chips, a chunk including a plurality of data bursts, first parity bits, and position bits from each of the plurality of memory chips; extracting, by the first ECC engine unit, a single data burst having an error from the plurality of data bursts using the position bits; and performing, by the first ECC engine unit, first error correction using the first parity bit corresponding to the extracted error data burst.

Memory system and method for error correction of memory

A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.

Memory device, memory module including the same, and memory system including the same

Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

Atomic memory access hardware implementations

Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.

Optoelectronic switches using on-chip optical waveguides

Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module () includes memory chips, and a demultiplexer register () electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into at least one virtual memory device in accordance with changing performance and/or energy efficiency needs. The demultiplexer register () is configured to receive a command indentifying one of the virtual memory devices and send the command to the memory chips of the identified virtual memory device. In certain embodiments, the memory chips can be dynamic random access memory chips.

Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules

Growing community of inventors

Seoul, South Korea

Jung Ho Ahn