International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Jung H Yoon

Antoine George Sater

Feng Xue

Phillip E Christensen

Jeffrey W Christensen

Daniel E Moore

Sumeet Kochar

Rosemary A Previti-Kelly

Tu T Dang

Juan Q Hernandez

Wen Wei Low

Steven B Gold

Yvonne Chii Yeo

John Edward Cronin

Ying Di Zhang

Timothy Harrison Daubenspeck

Sri Muthuthamby Sri-Jayantha

Mark Alan Lavin

Vinod Kamath

Stephen Ellinwood Luce

Vijayeshwar Das Khanna

Hien Phu Dang

James Gardner Ryan

Gerard McVicker

Fook-Luen Heng

Michael J Whitney

Maheswaran Surendra

Arpan Pravin Mahorowala

Carter W Kaanta

Gary S Ditlow

Daniel Lawrence Ostapko

John R Abernathey

Pei-ing P Lee

Robert A DiMarco

Gary P Viens

Denis J Poley

Vincent J Giancaspro

A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.

Sorting non-volatile memories

A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization

A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

A method for determining quality includes receiving supplier quality data from a supplier. The supplier quality data includes discrete quality data. The supplier quality data is for a quantity of a component supplied to a company or for a service provided on behalf of the company over a supplier measurement period. The method includes aggregating quality data from two or more suppliers. The quality data is for the supplied component or provided service over a baseline time period. The method includes determining a quality benchmark using the aggregated quality data and setting one or more alarm levels. The alarm levels are based on the quality benchmark of the aggregated quality data. The method includes determining supplier quality level for the supplier for the supplier measurement time period. The supplier quality is based on the supplier quality data. The method includes determining if the supplier quality data exceeds an alarm level.

Automated data-driven closed-loop-feedback method for adaptive and comparative quality control in a discrete data aggregation environment

An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.

Using persistent memory regions within memory devices to collect serial presence detect and performance data

A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottom area of the structure.

Structures to enhance cooling of computer memory modules

The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or next generation lithography techniques. The invention relates more particularly, but not by way of limitation, to lateral trimming of photoresist images.

Lateral-only photoresist trimming for sub-80 nm gate stack

In connection with the manufacture of chips having partitioned logic, a partitioned mask layout approach. This approach provides the chip exposure pattern as a set of partitions corresponding to macros or core functions and also handles glue logic and interconnect. A result of this approach is a simplified, cost-effective process that does not defer customization to other, potentially more time-consuming and inefficient tasks.

Partitioned mask layout

Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

Process for forming multi-level coplanar conductor/insulator films

A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

Bilayer metallization cap for photolithography

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Poughkeepsie, NY, United States of America

Jung H Yoon