Samsung Electronics Co., Ltd.

Jung-Gyu Lim

Shung-hyun Cho

Hee-Duck Park

Noh-byung Park

Noh-Buyng Park

A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a stop clock interrupt mode receives a stop clock interrupt signal and sets up and clears the stop clock interrupt mode according to a logic state of the stop clock interrupt signal. The control processor receives a signal representing an idle condition of the computer system from the idle detector, a signal for enabling idle detector control of the CPU stop clock interrupt mode and a signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The idle condition can be defined by a computer user according to a selection of predetermined times during which no user inputs are received by the computer system. The method includes monitoring the idle condition of the computer system, monitoring the signal for enabling idle detector control of the stop clock interrupt mode and monitoring the signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The stop clock interrupt signal is output having a logic state corresponding to the logic combination of the monitored signals.

Method and device for controlling a CPU stop clock interrupt

A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a stop clock interrupt mode receives a stop clock interrupt signal and initiates and terminates the stop clock interrupt mode according to a logic state of the stop clock interrupt signal. The control processor receives a signal representing an idle condition of the computer system from the idle detector, an alternate signal for idle detector control of the CPU stop clock interrupt mode, and a control signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The idle condition can be defined by a computer user according to a selection of predetermined times during which no user inputs are received by the computer system. The method includes monitoring the idle condition signal, monitoring the alternate signal for idle detector control of the stop clock interrupt mode and monitoring the control signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The stop clock interrupt signal is output having a logic state corresponding to the logic combination of the monitored signals.

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Kyungki-do, South Korea

Jung-Gyu Lim