Samsung Electronics Co., Ltd.

Jung Geun Jee

Eun Yeoung Choi

Hyung Joon Kim

Jung-Hwan Kim

Jin Gyun Kim

Hyun Namkoong

Dong-Kyum Kim

Su Hyeong Lee

Han-Vit Yang

Ji-Man Yoo

Eun Young Lee

Ki Hyun Hwang

Sang Yub Ie

Jae Myung Choe

Hun Hyeong Lim

Sung Youn Chung

Hyun Yong Go

Dong Kyum Kim

A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

Vertical-type memory device

An apparatus for generating 3D shape data of a showerhead includes: a data processor that generates data sets comprising information indicating values of a first distance between an upper surface of a wafer and a showerhead, information indicating positions on the wafer and information about a fluid flow physical quantity value and determines a function representing a relationship among the various information; an input unit that receives condition data comprising a target fluid flow physical quantity value for each of the positions; and a database that stores information about the function. The data processor obtains information about a second distance, which has the target fluid flow physical quantity value, between the upper surface of the wafer and the showerhead at each of the positions, extracts spatial coordinate information of a lower surface of the showerhead, and generates 3D shape data of the showerhead using the spatial coordinate information.

Apparatus and method for designing and manufacturing showerhead

A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer.

Method of manufacturing semiconductor device

A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Semiconductor devices and methods of manufacturing the same

Semiconductor devices

There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.

Method for manufacturing semiconductor device

There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.

Memory device

Growing community of inventors

Seoul, South Korea

Jung Geun Jee