Samsung Electronics Co., Ltd.

Jung-Geun Jee

Woong Hee Lee

Yong-woo Hyung

Won-Jun Jang

Ho-Min Son

Ki-Hyun Hwang

Bon-Young Koo

Chul-Sung Kim

Jin-Gyun Kim

Hun-Hyeoung Leam

Young-jin Noh

Jung-Hyun Park

Jae-Jong Han

Seok-Hoon Kim

Woo-Sung Lee

Sang-Kyoung Lee

Su-Jin Shin

Tae-Ouk Kwon

Taek-Jin Lim

Sang-Yub Ie

Sang-Hoon Lee

Eun-Young Lee

Kyung-Hyun Kim

Jae-young Ahn

Ji-Hoon Choi

Jung-Ho Kim

Hyeon-Deok Lee

Seung-Pil Chung

Hyoeng-ki Kim

Jae-Jin Shin

Dong-Kyum Kim

Guk-Hyon Yon

Bi-O Kim

Byong-Ju Kim

Sung-Hae Lee

Sung-kweon Baek

Choong-Kee Seong

Koong-Hyun Nam

Young-Sub You

Eun-Yeoung Choi

Hyun-Yong Go

Jae-Myung Choe

Jung-Yoon Ko

Jung-Hun No

An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.

Apparatus for atomic layer deposition and method of forming thin film using the apparatus

A computing system includes memory configured to store instructions and a nozzle library, and a processor configured to access the memory and to execute the instructions. The instructions cause the computing system to select at least one nozzle unit as a selected at least one nozzle unit based on the nozzle library and to place the selected at least one nozzle unit at corresponding location coordinates, to create multiple volume meshes for the process chamber, and to simulate the flow of the gas through the selected at least one nozzle unit in the process chamber based on the multiple volume meshes in the process chamber. The nozzle library includes information about multiple nozzle units of which each has multiple volume meshes formed therein. The nozzle units have different shapes from each other.

Computing system for gas flow simulation, and simulation method

In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.

Methods of manufacturing semiconductor devices including an oxide layer

A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Non-volatile memory device and method of manufacturing the same

A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

Non-volatile memory devices and methods of manufacturing the same

According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

Semiconductor device including a first core pattern under a second core pattern

A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.

Methods of forming a polysilicon layer and methods of manufacturing semiconductor devices

A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Method of forming nonvolatile memory device having floating gate and related device

In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.

Method of forming an insulation structure and method of manufacturing a semiconductor device using the same

A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.

Non-volatile memory device and method of fabricating the same

A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.

Method of forming a thin layer and method of manufacturing a semiconductor device

Growing community of inventors

Seoul, South Korea

Jung-Geun Jee