Skhynix Inc.

Samsung Electronics Co., Ltd.

Jung Dal Choi

Jung Shik Jang

Dong Hun Lee

In Su Park

Ki Hong Lee

Dong Sun Sheen

Jin Kook Kim

Sung Yong Chung

Mi Seong Park

Se Young Oh

Sung Hoon Lee

Ki Tae Park

Sung Bo Shim

Nam Jae Lee

Jae Woong Kim

Young Woo Park

Jeong Hwan Kim

Jae Duk Lee

Jang Won Kim

Jae Hoon Jang

Chang Seok Kang

Won Geun Choi

Jong-Yeon Kim

Soon Moon Jung

Woo Pyo Jeong

Ju Hyung Kim

Sung Kyu Jo

A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.

Semiconductor device with improved cell density and manufacturing method of the semiconductor device

The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Semiconductor memory device

The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.

Memory device storing logical page data and operating method of the memory device

There may be provided a method of manufacturing a semiconductor chip. A layer stack in which first material layers and second material layers are alternately stacked is formed on a semiconductor substrate that includes a chip region and a scribe lane region, and crack propagation guides are formed in a first portion of the layer stack within the scribe lane region.

Methods of manufacturing semiconductor chip including crack propagation guide

Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a stack structure; a source connection structure penetrating the stack structure; n first channel rows located at one side of the source connection structure, the n first channel rows including channel patterns; and n+k second channel rows located at the other side of the source connection structure, at least one channel row among the n+k second channel rows including dummy channel patterns, wherein the n and k are integers.

Semiconductor device and manufacturing method thereof

A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data.

Flash memory device and memory system comprising same

A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines.

Semiconductor memory device and programming method thereof

In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is applied to unselected word lines corresponding to unselected memory cell transistors of the selected transistor string positioned between the selected memory cell transistor and the other of the ground select transistor and the string select transistor.

Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line

Non-volatile memory devices have improved data storage reliability resulting from mirror-image programming techniques that operate to reduce coupling noise between adjacent memory cells within a memory array. The adjacent memory cells include a first pair of memory cells and a second pair of memory cells. A program control circuit is provided to support mirror-image programming of the first and second pairs of memory cells when the two pairs of memory cells are storing the same 3-bit data.

Growing community of inventors

Gyeonggi-do, South Korea

Jung Dal Choi