Samsung Electronics Co., Ltd.

Sung Woo Electronics Co., Ltd.

Jung-Dal Choi

Chang-Hyun Lee

Jong-Sun Sel

Ki-Tae Park

Jae-Sung Sim

Chang-Seok Kang

Young-Woo Park

Yoo-Cheol Shin

Kyu-Charn Park

Sung-Hoi Hur

Ju-Hyung Kim

Chang-seok Kang

Yong-Sik Yim

Byoung-Woo Ye

Hong-Soo Kim

You-Cheol Shin

Choong-Ho Lee

Sang-Hun Jeon

Jin-taek Park

Jang-Hyun You

Jin-Taek Park

Joon-Hee Lee

Sung-Il Chang

Dong-Uk Choi

Hyun-Suk Kim

Byeong-In Choe

Jong-woo Park

Yong-Joon Choi

Seong-Soon Cho

Sung-Kyu Jo

Won-Hong Lee

Byeung-Chul Kim

Hwa-Kyung Shin

Wang-Chul Shin

Uk-Jin Roh

Young-Ho Lim

Hee-Soo Kang

Won-Cheol Jeong

Jae-Kwan Park

Sun-Il Shim

Dong-jun Kim

Sung-Nam Chang

Byung-Kwan You

Kang-Deog Suh

Won-Seok Jung

Kwang-Shik Shin

Se-Hoon Lee

Sun-Jung Kim

Dong-Seog Eun

Hyung-Kyu Yim

Chany-Hyun Lee

Hong-Suk Kwack

Jang-Sik Lee

Vie-Na Kim

Ju-Hyuck Chung

Sang-jin Park

Jong-seob Kim

Sung-il Park

Jae-Duk Lee

Ki-Hwan Choi

Yun-Seung Shin

Sung-hoon Lee

Jong-Ho Park

Hyong-Gon Lee

Jong-Won Kim

Jin-Ki Kim

Hong-soo Kim

Jong-Han Kim

Kwang-soo Seol

Seung-hyun Lim

Eun-Young Choi

Woong-hee Sohn

Seung-Hyun Moon

Min-Cheol Park

Chung-Il Hyun

Dae-Woong Kang

Ji-Hwon Lee

Byeong-In Choi

Seung-Hyun Lim

Heung-Kwun Oh

Jae-Young Do

Min-Tai Yu

Jung-Young Lee

Sang-Bin Song

Dong-soo Chang

Woong-Moo Lee

Sung-Bu Jun

Sok-guen Chang

Kang-deok Suh

Sung-Tae Ahn

A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer.

Non-volatile memory devices and methods of operating the same

In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

Memory devices including vertical pillars and methods of manufacturing and operating the same

A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

Nonvolatile memory devices

Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.

Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure

A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.

Non-volatile memory devices

A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps

Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. The first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect gate electrodes of the first enhancement-mode transistor and one of the second plurality of depletion-mode transistors.

Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.

Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices

A semiconductor device includes a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are provided on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Methods of fabricating semiconductor devices with sidewall conductive patterns

A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

Memory device and method of fabricating the same

Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

Methods of fabricating flash memory devices having shared sub active regions

A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.

Semiconductor device capable of suppressing short channel effect

Growing community of inventors

Gyeonggi-do, South Korea

Jung-Dal Choi