Taiwan Semiconductor Manufacturing Comp. Ltd.

Jung-Chi Jeng

Ru-Shang Hsiao

Sung-Hsin Yang

Chih-Mu Huang

I-Chih Chen

Ying-Hao Chen

Wen-Chang Kuo

Chi-Cherng Jeng

Ling-Sung Wang

Chen-Chieh Chiang

Ying-Lang Wang

Shyh-Wei Cheng

Yun Shen Chang

Cheng-You Tai

Volume Chien

Tsung-Han Tsai

Huang-Ta Huang

Yueh-Ching Chang

Tsung Jing Wu

Ching-Hwanq Su

Chih-Kang Chao

Yi-Ting Chen

Chih-Cherng Jeng

Yan-Hua Lin

Ru-shang Hsiao

Yu-Shen Shih

Zhi-hong Chung

Yi Ping Chao

A method for forming a semiconductor structure includes following operations. First fins are formed in a first region of a substrate, and second fins are formed in a second region of the substrate. Widths of the first fins are greater than widths of the second fins. An isolation structure is formed over the substrate. A first ion implantation is performed on the first fins. A portion of the isolation structure is removed to expose a portion of each first fin and a portion of each second fin. The widths of the first fins are equal to or less than the widths of the second fins after the removing of the portion of the isolation structure. A 3D capacitor is formed in the first region, and a FinFET device is formed in the second region. The 3D capacitor includes the first fins, and the FinFET device includes the second fins.

Semiconductor structure including 3D capacitor and method for forming the same

A semiconductor image-sensing structure includes a semiconductor substrate having a sensor region and a circuitry region, a plurality of fin structures disposed in the circuitry region, a mesa structure disposed in the sensor region, a first gate structure disposed over the plurality of fin structures in the circuitry region, and a second gate structure disposed over the mesa structure in the sensor region. The plurality of fin structures and the mesa structure include a same semiconductor material.

Semiconductor image-sensing structure and method for forming the same

A container for receiving a semiconductor device is provided. In one embodiment, the wafer holder assembly includes a first wafer holder with a plurality of first fingers arranged in a first common horizontal plane and a second wafer holder with a plurality of second fingers arranged in a second common horizontal plane. The first wafer holder and the second holder are configured to move relative to each other in a vertical direction, and the first wafer holder and the second holder are configured to rotate relative to each other around a vertical axis.

Wafer holder assembly

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. The semiconductor device includes an isolation structure in the semiconductor substrate. The isolation structure surrounds an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate is across the active region and extends onto the isolation structure. The semiconductor device includes a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure.

Semiconductor device with gate

Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

Semiconductor devices and methods for increased capacitance

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

High voltage device

In an embodiment, a device includes: an isolation region on a substrate; a fin structure protruding from between adjacent portions of the isolation region, the fin structure including a plurality of fins and a mesa, a channel region of the fin structure having a first portion in the fins and having a second portion in the mesa, the fins and the mesa being a continuous semiconductor material, the mesa having a greater width than the fins; and a first gate structure on the fin structure, the first gate structure extending along the first portion of the channel region in the fins and extending along the second portion of the channel region in the mesa.

Semiconductor device and method

Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

FinFET MOS capacitor

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

Input/output devices

Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a substrate including a core device region and an input/output (I/O) device region, a plurality of core devices in the core device region, each of the plurality of core devices including a first active region extending along a first direction, and a first plurality of input/output (I/O) transistors in the I/O device region, each of the first plurality of I/O transistors including a second active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction and the second active region includes a second width along the second direction. The second width is greater than the first width.

High voltage devices

A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first three-dimensional semiconductor structure of a first conductivity type protruding from a surface of the semiconductor substrate. The semiconductor device includes a second three-dimensional semiconductor structure of a second conductivity type protruding from the surface of the semiconductor substrate. The semiconductor device includes a first transistor having a first source/drain structure formed in the first three-dimensional semiconductor structure, a second source/drain structure formed in the second three-dimensional semiconductor structure, a first gate structure straddling a first portion of the first three-dimensional semiconductor structure and a first portion of the second three-dimensional semiconductor structure, and a second gate structure straddling a second portion of the second three-dimensional semiconductor structure.

Semiconductor devices and methods of manufacturing thereof

Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

Fabrication of long gate devices

A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.

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Tainan, Taiwan

Jung-Chi Jeng