Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Jung-Chi Huang

Wen-Juh Kang

Liang-Hung Chen

Yen-Chung Chen

Ming-Hsien Tsai

Chen-Yang Pan

Shih-Chi Wu

Meng-Chin Tsai

A method and associated processing module for an interconnection system, providing a pre-tap tuning directing and a post-tap tuning directing. The interconnection system includes a transmitter filter and a receiver equalizer; the transmitter filter performs filtering according to a pre-tap and a post-tap, and the receiver equalizer performs equalization according to an equalizer tap. The pre-tap tuning directing includes: forming an indicative pattern with a plurality of data samples and a transition sample from an equalized signal, comparing if the indicative pattern matches predetermined pattern(s), and accordingly directing whether the pre-tap is incremented/decremented. The post-tap tuning directing selects whether the post-tap is incremented/decremented according to a positive/negative sign of the equalizer tap.

Method and associated processing module for interconnection system

Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.

Eye diagram scan circuit and associated method

A receiver circuit receives an incoming signal and accordingly provides an internal signal, and includes an equalizer, a slicer module and a counter module. The equalizer provides a signal level according to the incoming signal, the slicer module compares if the internal signal exceeds a level range; according to comparison result, the counter module provides a signal quality indication capable of indicating whether a bit error rate of signal receiving is greater than a predetermined reference bit error rate. One of an upper bound and a lower bound of the level range can equal the signal level, a distance between the upper bound and the lower bound is set according to a reference signal-to-noise ratio which associates with the reference bit error rate.

Receiver circuit

A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.

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Changhua County, Taiwan

Jung-Chi Huang