Kendin Communications

Kendin Semiconductor, Inc.

Jung-Chen Lin

Menping Chang

Lawerence W Mo

A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal. A method of phase locking an output clock with a reference clock includes, checking the occurrence of an aliased condition, increasing the speed of the output clock in response to an aliased condition, and increasing the speed of the output clock if the output clock is lagging the reference clock and decreasing the speed of the output clock if the output clock is leading the reference clock.

Delay cell

Delay locked loop for sub-micron single-poly digital CMOS processes

Systems and methods are described for adaptive equalizers. A circuit adapted to transform an equalizer input signal at a receiver to approximate an output signal at a transmitter includes an equalizer, a phase matching loop coupled to the equalizer, and an amplitude locking loop coupled to the equalizer. The equalizer can include a number of coarse band segments to provide coarse adjustment, at least one of which includes a number of fine band segments to provide fine adjustment. The systems and methods provide advantages in that multiple cable lengths can be serviced by a single equalizer, variations in the low frequency gain and the location of the zero point due to variations in manufacture and operating temperature are obviated, and a suitable gain can be provided at much higher frequencies.

Adaptive equalizer

Systems and methods are described for implementing a backplane in the context of a stack of networking hubs based on a backplane connecter and for carrying out a method of configuring and terminating the backplane. A backplane connector includes a first voltage source; a plurality of connector contacts; a plurality of termination resistors, a first end of the plurality of termination resistors being coupled to the plurality of connector contacts; a first switch located between the first voltage source and a second end of the plurality of termination resistors; a first logic circuit coupled to the first switch, the first logic circuit closing the first switch when a layer composed by the backplane connector is both i) active and ii) either a top layer in a stack composed by the layer or a bottom layer in the stack. The systems and methods provide advantages in that a plurality of stackable network hubs can be economically coupled together with automatic impedance matching and the ability to power down one or more layers in a stack without disrupting data flow between other layers in the stack.

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Cupertino, CA, United States of America

Jung-Chen Lin