United Microelectronics Corp.

Jung-Chao Chiou

Chuan-Fu Wang

Benjamin Szu-Min Lin

Hsiao-Pang Chou

Jhy-Jyi Sze

Chien-Li Kuo

King-Lung Wu

Te-Yuan Wu

Chin-Hui Lee

A method for forming an opening is provided. The method contains forming a dielectric layer on the substrate. The dielectric layer is patterned to form a first-stage opening. A carbonic-polymer (C-polymer) concentration controlling treatment is performed to obtain a proper C-polymer concentration, which can be raised, reduced, or even down to a zero concentration. After the proper C-polymer concentration is obtained, a next-stage opening is formed by another step of etching. The C-polymer concentration controlling treatment and the etching process with a new condition for each step can be repeated until a desired opening is formed.

Method for forming an opening

This invention relates to a method of forming a landing pad on a semiconductor wafer comprising a silicon substrate, a dielectric layer, a passivation layer and a photo-resist layer. The photo-resist layer comprises a hole penetrating to the surface of the passivation layer which defines the position of the landing pad. An anisotropic etching through the hole is performed to vertically remove the passivation layer and a predetermined thickness of the dielectric layer under the hole to form a recess, and then the photo-resist layer is removed. A filling layer is deposited on the passivation layer and the recess. An etch-back process is performed to remove the filling layer on the bottom portion of the recess and form a circular spacer on the surrounding portion of the recess. Another anisotropic etching is performed to vertically remove the dielectric layer under the recess and down to the surface of the silicon substrate which forms a plug hole, over which the circular spacer is used as a hard mask. Lastly, a conductive layer is deposited to completely fill the recess and the plug hole which forms the landing pad.

Method of forming a landing pad on a semiconductor wafer

The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole. Finally, a spacer is formed using an insulating material on the walls of the node contact hole to complete the node contact hole. The spacer completely covers the walls of the two bit lines within the node contact hole but the surface of the silicon substrate exposed at the bottom of the node contact hole is not completely covered by the spacer.

Method of forming a node contact hole on a semiconductor wafer

A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole. A second dry etching process is used to etch the second conductive layer using the photo resist layer as a mask so as to form the storage node. Finally, the photo resist layer is removed.

Method of fabricating a DRAM storage node on a semiconductor wafer

A method for forming an opening in a semiconductor device is provided. A silicon-oxy-nitride layer is formed on a dielectric layer and then a photoresist layer with a first opening is formed on the silicon-oxy-nitride layer. A polymer film is formed on sidewalls of the first opening. A second opening narrower than the first opening is formed in the dielectric layer with the photoresist layer and the polymer film.

Method for forming opening in a semiconductor device

A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure after the removal of SiON by phosphoric acid (H,PO,) is disclosed. The method includes: Providing a semiconductor substrate having a semiconductor structure formed thereon; forming an interlayer dielectric layer over the semiconductor structure; patterning the interlayer dielectric layer; depositing an amorphous-silicon (a-Si) layer over the interlayer dielectric layer; depositing a SiON layer on the a-Si layer; patterning the SiON layer and the a-Si layer layer; removing the SiON layer by H,PO,wet etching; forming a s-HSG silicon layer over the patterned a-Si layer; depositing a conformal interpoly dielectric layer along a surface of the resulting structure; and finally forming a polysilicon layer over the interpoly dielectric layer.

Removal of silicon oxynitride on a capacitor electrode for selective hemispherical grain growth

A method of fabricating a bottom electrode for a capacitor is described in which a dielectric layer is formed on a substrate already comprising an isolation layer, an etching stop layer and a landing pad. Bit line structures and spacers are further formed on the dielectric layer. A node contact window opening is formed in the dielectric layer, exposing the landing pad, and a conformal first conductive layer is formed on the substrate. After a specially patterned mask layer is formed and the exposed first conductive layer is removed, an extended portion is formed connecting to the conductive layer to complete the fabrication of the columnar bottom electrode for a capacitor.

Fabrication method for bottom electrode of capacitor

A method for forming a capacitor structure of semiconductor is disclosed. The method includes the following steps. First of all, a first oxide layer is deposited. A first nitride layer is formed. Consequentially, a portion of the first nitride layer and a portion of the first oxide layer are all etched. Then, the first polysilicon layer is formed. The portion of the first polysilicon layer is reduced to a specified thickness. Next, boron phosphorus silicon glass layer blankly and conformably is formed. Then, a portion of said boron phosphorus silicon glass layer is etched. A second polysilicon layer is deposited. Next, a portion of the second polysilicon layer is etched back. Next, the boron phosphorus silicon glass layer is etched. Then, the first polysilicon layer is etched back. A second nitride layer is formed. Next, a second oxide layer is deposited. Finally, a conductive layer is formed as a top plate of capacitor, whereby a capacitor structure is completed and there are a top plate and a bottom plate.

Forming a capacitor structure of a semiconductor

This invention provides a method of forming a node contact with self-alignment on a semiconductor wafer. The wafer comprises a substrate, a dielectric layer, and a first and a second bit lines. A first side wall of the first bit line is adjacent to a second side wall of the second bit line and comprises a first region and two second regions adjacent to the first region. The distance between the first region and the second side wall is greater than a predetermined value and the distance between the two second regions and the second side wall is less than the predetermined value. A second insulating layer is formed on the dielectric layer and two bit lines to form a groove over the gap between the first region and the second side wall. A first anisotropic etching is performed to extend the bottom of the groove down to the dielectric layer. The remaining second insulating layer around the groove forms a spacer, and the remaining second insulating layer in the gaps between the two second regions and the second side wall still completely covers the surface of the two gaps. A second anisotropic etching process is performed to remove the dielectric layer at the bottom of the groove in a vertical direction down to the substrate so as to form the node contact.

Method of forming a node contact of a DRAM's memory cell

A method for forming a cylinder-shaped capacitor for dynamic random access memories (DRAMs) is disclosed. The method includes forming a silicon layer having a gap therein over a semiconductor substrate, followed by conformably forming a first dielectric layer on the silicon layer. Next, a second dielectric layer is formed on the first dielectric layer, filling the gap. After etching back the second dielectric layer, the first dielectric layer is removed until the silicon layer is exposed. Then the second dielectric layer is removed, and the silicon layer is etched using the first dielectric layer as a mask, thus forming a cylinder-shaped structure of the silicon layer over the substrate.

Method for forming a cylinder-shaped capacitor using a dielectric mask

A method of fabricating a dual cylindrical capacitor. On a substrate having a conductive region, an insulation layer is formed with an opening which exposes the conductive region. A conductive layer is formed over the insulation layer to fill the expose conductive region. A mask is formed to cover a part of the conductive layer aligned over the perimeter of the opening. A part of the conductive layer is removed to form two protrusions on the surface of the remaining conductive layer aligned over the perimeter of the opening. A spacer is formed on each side wall of the protrusions. Using each spacer as a mask, the remaining conductive layer is further removed by self-stop etching process. The spacer is removed, and a dielectric layer is formed to cover the conductive layer. Another conductive layer is formed to cover the dielectric layer.

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Hsin-Chu, Taiwan

Jung-Chao Chiou