Nanochips, Inc.

Chungbuk National University Industry-academic Cooperation Foundation

Other

Changbuk National University Industry-academic Cooperation Foundation

Jung Bum Choi

Jong Jin Lee

Hun Woo Kye

Chang Keun Lee

Jae Ho Hwang

Sang Jin Kim

Bok Nam Song

Rae-Sik Chung

Min Sik Kim

Bok-Nam Song

Seung-Jun Shin

Seung Jun Shin

Cang Keun Lee

The present system relates to a system architecture that uses a single electron transistor (SET) to analyze base sequences of deoxyribonucleic acid (DNA) at ultra high speed in real time. DNA represents the entire body of genetic information and consists of nucleotide units. There are a total of four types of nucleotides, and each nucleotide consists of an identical pentose (deoxyribose), phosphate group, and one of four types of bases (Adenine: A, Guanine: G, Cytosine: C, Thymine: T). A and G are purines having a bicyclic structure while C and T are pyrimidines having a monocyclic structure. Each has a different atomic arrangement, which signifies a different charge distribution from one another. Therefore, a system comprising a single electron transistor that is very sensitive to charges, a probe of a very small size that reacts to one nucleotide very effectively, and an extended gate that connects the SET with the probe, can be used to analyze DNA base sequences at ultra high speed in real time.

Ultra high speed and high sensitivity DNA sequencing system and method for same

The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device. Further specifically, present invention relates to a multi-quantum dot device including a channel configured by patterning the top silicon layer of an SOI wafer to have a P-type silicon region formed by connecting a transversal region and a longitudinal region and a plurality of N-type silicon regions; gates including a plurality of tunneling barrier gates, an end of each tunneling barrier gate is positioned on the top of a transversal side of an intersection of the transversal region and the longitudinal region of the P-type silicon region to locally control a potential in the channel; a plurality of coupling gates, an end of each coupling gate is positioned on the top of a point between the intersection and another intersection adjacent to the intersection to locally control the potential in the channel; and a plurality of sensor gates, an end of each sensor gate is positioned on the top of a center of the intersection to sense a state of a quantum dot formed at the intersection; and an inversion layer gate formed on the top of the P-type silicon region to control free electron density.

Multiple quantum dot device and a production method for the device

The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.

Nanoscale multi-junction quantum dot device and fabrication method thereof

The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

Single electron transistor operating at room temperature and manufacturing method for same

Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET.

Multiple valued dynamic random access memory cell and thereof array using single electron transistor

Provided herein is an MV DRAM device for storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, where the gate of the transistor is connected to the ground voltage.

Multiple-valued DRAM

The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single-electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof.

Room temperature-operating single-electron device and the fabrication method thereof

The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs) having the same pattern and as many field effect transistors (FETs) as the number of the single electron transistors and performs operations on multi-valued signals using Coulomb oscillation that is the unique characteristic of SET to enable conversion of a single logic circuit to four basic logic circuits of NAND, OR, NOR and AND gates and a device using the same.

Growing community of inventors

Cheongju-si, South Korea

Jung Bum Choi