Samsung Electronics Co., Ltd.

Sasung Eelctronics Co., Ltd.

Jung-Bae Lee

Chul-Woo Park

Sung-Hoon Kim

Hoe-Ju Chung

Kyu-Hyoun Kim

Yun-sang Lee

Hyuk-Joon Kwon

Jung-Sik Kim

Byong-mo Moon

Seong-young Seo

Yun-Sang Lee

One-gyun La

Youn-Sik Park

Joo-sun Choi

Soo-In Cho

Cheol Su Kim

Jae-Yoon Sim

Sang-Ho Shin

Mee-Hyun Ahn

Chan-Yong Lee

Chul-woo Park

Young-Soo Sohn

So-Young Kim

Dong-jin Lee

Jong-Pil Son

Jong-hyun Choi

Hak-soo Yu

Ho-Cheol Lee

Chul-Sung Park

Won-Seok Lee

Jae-Youn Youn

Jung-hwan Choi

Dong-Yang Lee

Young-Sun Min

Yoon-jae Lee

Chi-Sung Oh

Duk-Ha Park

Sang-bo Lee

Kyu-hyoun Kim

Chang-Yong Lee

Sang-Jae Rhee

Won-Chang Jung

Tae-seong Jang

Kwang-Sook Noh

Sung-Min Yim

Sung-Geun Lee

Chan-yong Lee

Jong-Eon Lee

Hyun-chul Yoon

Jun-phyo Lee

Sang-kyun Park

Won-chang Jung

Dae-hyun Chung

Jae-hyung Lee

Hyung-Sik You

Jin-Kyoung Jung

Taek-Seon Park

Kun-tae Kim

Hong-joon Park

Hong-Joon Park

Sung-ryul Kim

Min-Jeung Cho

Jing-Man Han

A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a complementary bit line connected to a plurality of memory cells of a second memory block, a first switch configured to connect the bit line to the sense amplifier, and a second switch configured to connect the complementary bit line to the sense amplifier. The first switch is configured to electrically separate the bit line from the sense amplifier when the second memory block performs a refresh operation.

Bit-line sense amplifier, semiconductor memory device and memory system including the same

In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed.

Memory device and method of refreshing in a memory device

An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.

Memory devices with selective error correction code

A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.

Semiconductor memory device performing a refresh operation, and memory system including the same

A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band.

Semiconductor memory device storing refresh period information and operating method thereof

A method of refreshing a semiconductor memory device includes performing a first refresh operation for memory cells included in a memory cell array, and determining whether a command other than a refresh command is applied to the semiconductor memory device in a refresh cycle of the first refresh operation. The method further includes continuing to perform the first refresh operation when a command other the refresh command is applied to the semiconductor memory device in one refresh cycle of the first refresh operation, and performing a second refresh operation when a command other than the refresh command is not applied to the semiconductor memory device in one refresh cycle of the first refresh operation. A refresh time of the second refresh operation is greater than a refresh time of the first refresh operation.

Semiconductor memory device including refresh control circuit and method of refreshing the same

A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Semiconductor memory device having improved refresh characteristics

A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

Refresh circuit of a semiconductor memory device and refresh control method of the semiconductor memory device

Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

Semiconductor devices and semiconductor packages

A method and an apparatus for connecting a network in a portable terminal. The method for connecting a network in a portable terminal includes searching a network from which a signal is received, receiving network identifying information from the searched network, retrieving connection information corresponding to the network identifying information, from network connection information stored in the portable terminal in advance, and setting the retrieved network connection information as the network connection information of the portable terminal.

Apparatus and method for connecting network in portable terminal

Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.

Sub-word-line driving circuit, semiconductor memory device having the same, and method of controlling the same

An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

Internal voltage generating circuit for semiconductor device

A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Memory system and command handling method

A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal.

Semiconductor memory devices with interface chips having memory chips stacked thereon

A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

Memory system, memory device and command protocol

Growing community of inventors

Gyeonggi-do, South Korea

Jung-Bae Lee