Skhynix Inc.

Other

Jung Ae Kim

Jee Yul Kim

Sung Jin Park

Jeen Park

Yeong Dong Gim

Eun Jae Ock

Beom Rae Jeong

Tae Ha Kim

Sung Ae Jung

Jang Hyun Kim

Young-hwa Chung

Neung Hwa Park

Provided herein is an electronic device including: a host configured to judge a possibility of occurrence of an SPO based on driving information of a transportation device, and determine an operation mode of a storage device to be an SPO protection mode or a performance mode based on the possibility of an SPO occurrence; a buffer memory device configured to temporarily store user data received from the host; a memory device configured to store the user data output from the buffer memory device; and a memory controller configured to set a size of the buffer memory device depending on the determined operation mode and to control the buffer memory device to output at least a part of the user data temporarily stored in the buffer memory device to the memory device based on an amount of the buffer memory device used.

Electronic device and method of operating the same

The present technology relates to an electronic device. According to the present technology, a memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to generate operation voltages for the plurality of memory cells and transfer the operation voltages to the memory block through bit lines and word lines, and a control logic configured to control, based on temperature information of the memory device, the peripheral circuit to perform a low temperature management operation of increasing a temperature of the memory device. The peripheral circuit may transfer the operation voltages while limiting transferal of a local word line apply voltage to be applied to the memory block through the word lines in response to the low temperature management operation, the local word line apply voltage being included in the operation voltages.

Memory device and method of managing temperature of the same

A storage device may transmit a command set to a memory, set a plurality of flag bits based on transmission status of a plurality of commands included in the command set, respectively, and determine whether an error occurred in the process of transmitting the command set to the memory based on the plurality of flag bits. Each of the plurality of flag bits has a first value or a second value, and the command set includes a reset command, a command set start command, and a command set end command.

Storage device for determining successful transmission of commands and methods of operation

A controller controls a semiconductor memory device including a plurality of pages. The controller includes a command generator configured to generate a command for controlling a program operation or a read operation of a semiconductor memory device, and a data recovery manager configured to generate parity data corresponding to a weak page among a plurality of pages included in the semiconductor memory device and recover data programmed to the weak page.

Controller and method of operating the same

A storage device performs a read operation, based on a temperature measured in a program operation or an erase operation. The storage device includes: a memory device including a plurality of memory blocks, the memory device measuring a temperature in a program operation or an erase operation; and a memory controller for setting an area in which the measured temperature is to be stored in the memory device, and controlling a read operation to be performed in the memory device. When a read command for a selected page among a plurality of pages included in each of the plurality of memory blocks is received from the memory controller, the memory device determines a read voltage and a pass voltage based on a temperature corresponding to the selected page and performs a read operation on the selected page by using the read voltage and the pass voltage.

Storage device and operating method thereof

A memory system includes a memory device including plural memory groups, each memory group including plural non-volatile memory cells; and a controller configured to transmit a command to the memory device so that the memory device performs a data input/output operation within at least one memory group among the plural memory groups, receive a response for the command and a status data regarding the at least one memory group from the memory device, and determine whether the data input/output operation has succeeded or failed based on the response and the status data.

Apparatus and method for checking an error of a non-volatile memory device in a memory system

A memory device is provided to include: a plurality of memory cells; a peripheral circuit configured to perform an operation on the plurality of memory cells; a temperature circuit configured to measure a temperature of the memory device; a monitoring component configured to generate, based on whether a measured temperature is within a reference range, monitoring information representing an operation mode that is either a normal mode in which the operation is performed or a protection mode in which the operation is suspended; and an operation controller configured to output a signal for controlling the operation according to the monitoring information. The monitoring component is further configured to store the monitoring information and output the monitoring information to the operation controller in response to receiving the measured temperature from the temperature circuit.

Memory system and operating method thereof

A memory controller and a method of operating the same may provide recovery from a Sudden Power-Off (SPO). The memory controller may control a memory device including a plurality of memory blocks, each memory block having a plurality of pages. The memory controller may include a dummy program controller configured to, after an SPO has occurred while a program operation was being performed on a page of the memory device, control a dummy program operation for recovering from the SPO; a parity data controller configured to control resetting and generation of parity data for chipkill decoding based on pages on which the dummy program operation is determined to be performed; and a valid data controller configured to control movement of valid data based on a number of pages on which the dummy program operation is to be performed.

Memory controller and method of operating the same

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, when result data obtained by derandomizing data included in a flag area is different from reference data after a random data unit is derandomized based on a seed, it is possible to detect an error occurring in the seed in a process of derandomizing the data and to prevent malfunction of firmware in advance by searching for a target seed and derandomizing the random data unit based on the target seed.

Memory system, memory controller, and method of operating memory system

Embodiments of the disclosure relate to a memory system and an operating method thereof. The memory system may decrypt first firmware which is stored in the memory device and is encrypted using a symmetric-key encryption algorithm, with a first key stored in the memory device, may generate a second key based on second firmware, which is obtained by decrypting the first firmware, first data stored in a first area in the memory controller, and second data stored in a second area in the memory device, and may drive the second firmware when the first key and the second key are the same.

A memory controller includes a read only memory (ROM) suitable for outputting a ROM code to execute firmware in response to fuse data and a control processor suitable for executing the firmware in response to the ROM code. A memory system includes the memory controller and a storage device storing data.

Memory controller and memory system

A data storage device includes: a storage configured to store flag information on attributes, each attribute corresponding to a revision version, and firmware comprising register setting information and firmware execution code branch information for each attribute; and a controller configured to read the flag information and the firmware from the storage to execute the firmware according to the flag information.

Data storage device, operation method thereof, and firmware providing server therefor

A memory system includes a nonvolatile memory device including a CAM (content addressable memory) region; and a controller including a random access memory which stores an initial setting parameter of the nonvolatile memory device and a control unit which controls an initializing operation for a setting parameter of the nonvolatile memory device stored in the CAM region, wherein the control unit includes a parameter determination circuit which determines whether the initializing operation has succeeded or not, by comparing a verify parameter received from the nonvolatile memory device and the initial setting parameter.

A data storage apparatus includes a storage configured to include a storage configured to include at least one die including a plurality of planes, wherein each of the plurality of planes contains a set of a plurality of memory blocks, each including a plurality of pages configured of a plurality of memory cells; and a controller configured to: control data input to and output from the storage according to a request received from a host apparatus, receive a plurality of read requests including respective access addresses and access sizes from the host apparatus, generate one or more paired read requests from among the plurality of read requests so that a region to be accessed in one read operation is minimized, and determine a read option for each of the paired read requests.

Data storage apparatus, operating method thereof, and storage system having the same

A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.

Growing community of inventors

Gyeonggi-do, South Korea

Jung Ae Kim