Samsung Electronics Co., Ltd.

Junehong Park

Chiweon Yoon

Jayang Yoon

Chihyun Kim

Hyeongdo Choi

Sangsoo Park

Kichang Jang

Dojeon Lee

A non-volatile memory device includes a memory cell array including memory cells coupled to word lines, a boost circuit that receives an external power supply voltage and generate a boosted voltage based on the external power supply voltage, a regulator that generates a regulated voltage based on the external power supply voltage, and a control logic that controls word line voltages provided to the word lines. The control logic performs plural program loops in a program operation for the memory cell array. The control logic provides an adjacent word line voltage to an adjacent word line that is adjacent to a selected word line. In a first section of the program loops, the control logic provides the regulated voltage as the adjacent word line voltage, and in a second section of the program loops, the control logic provides the boosted voltage as the adjacent word line voltage.

Non-volatile memory device, storage device having the same and operating method of non-volatile memory device

In a method of operating a memory device, a first operation is performed on a memory block by applying first driving voltages to a plurality of wordlines. After the first operation is completed, a first recovery operation in which the first driving voltages applied to the plurality of wordlines are discharged is performed. After the first recovery operation is completed, a second operation is performed on the memory block by applying second driving voltages to the plurality of wordlines. In the first recovery operation, first charges among a plurality of charges stored by the first driving voltages are stored in a charge recycling memory block connected to at least one charge recycling wordline. In the second operation, the second driving voltages are applied to the plurality of wordlines using the first charges stored in the charge recycling memory block.

Method of operating memory device and memory device performing the same

A semiconductor device includes a first voltage generating circuit configured to output a first voltage based on temperature; an analog-to-digital converter configured to convert the first voltage into a temperature code; a code conversion logic configured to output an offset code and a level code of a temperature section which the temperature belongs among temperature sections based on the temperature code; an offset voltage generating circuit configured to output an offset voltage based on the offset code; a second voltage generating circuit configured to output a second voltage having a constant value within a temperature section based on the level code; and a temperature compensation voltage generating circuit configured to receive the first voltage, the second voltage, the offset voltage, and a feedback voltage and output a temperature compensation voltage, the feedback voltage based on the first voltage, the second voltage, and the offset voltage.

Semiconductor device

Growing community of inventors

Suwon-si, South Korea

Junehong Park