Electronics and Telecommunications Research Institute

June Young Chang

Han Jin Cho

Nak Woong Eum

Seong Mo Park

Mi Young Lee

In San Jeon

Young Hwan Bae

Kyoung Seon Shin

Moo Kyoung Chung

Sang Heon Lee

Won Jong Kim

Ju Yeob Kim

Guee Sang Lee

Provided are a network load reducing method and a node structure for a multiprocessor system with a distributed memory. The network load reducing method uses a multiprocessor system including a node having a distributed memory and an auxiliary memory storing a sharer history table. The network load reducing method includes recording the history of a sharer node in the sharer history table of the auxiliary memory, requesting share data with reference to the sharer history table of the auxiliary memory, and deleting share data stored in the distributed memory and updating the sharer history table of the auxiliary memory.

Network load reducing method and node structure for multiprocessor system with distributed memory

There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Distributed video coding apparatus and method capable of controlling encoding rate

Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2&#xd7;1 multiplexers connected in a matrix form consisting of rows and columns. The 2&#xd7;1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Crossbar switch architecture for multi-processor SoC platform

Growing community of inventors

Daejeon, South Korea

June Young Chang