Micron Technology Incorporated

Skhynix Inc.

Sk Hynix Memory Solutions Inc.

Intel Corporation

Round Rock Research, LLC

June Lee

Fan Zhang

Yu Cai

Dean K Nobunaga

Chih Liang Chen

David J Pignatelli

Chenrong Xiong

Haibo Li

Fred Jaffin, Iii

Michele Piccardi

Shuai Xu

Aman Bhatia

HyungSeok Kim

Naveen Kumar

Tomoko Ogura Iwasaki

Scott Anthony Stoller

Qisong Lin

Scott N Gatzemeier

Jun Shen

Arvind Muralidharan

Tommaso Vali

Aaron S Yip

Jung Sheng Hoei

Eric N Lee

Lingqi Zeng

Karl David Schuh

Terry M Grunzke

Xiaojiang Guo

Dheeraj Srinivasan

Daniel J Hubbard

Umberto Siciliani

Ali Mohammadzadeh

Daniel R Elmhurst

Jiewei Chen

Naveen Kaushik

Luyen Tien Vu

Andrea Giovanni Xotta

Mithun Kumar Ramasahayam

Yan Zhang

Rohitkumar Makhija

Guido Luciano Rizzo

Shi Yin

Jaesung Sim

Fred Jaffin

In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.

Low power management for sleep mode operation of a memory device

Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Dynamic latches above a three-dimensional non-volatile memory array

Double single level cell program in a memory device

A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

Independent plane architecture in a memory device

Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

Capacitor in a three-dimensional memory structure

A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

Voltage regulation

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Asynchronous/synchronous interface

Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of the plurality of blocks, updating wordline information of a plurality of wordlines in the counted block when the number of reads exceeds a block read count threshold, selecting a wordline from the plurality of wordlines, determining an error rate of a neighbor wordline to the selected wordline, and reclaiming data in the block when the error rate exceeds an error threshold.

Hybrid read disturb count management

A memory device includes a plurality of memory blocks, each block with multiple memory cells. Each memory block has an address and a block read threshold. The plurality of memory blocks is partitioned into clusters based on block read thresholds. The memory device also has a look-up table for storing information associating each cluster of memory blocks with a corresponding cluster read threshold. The look-up table further includes cluster boundaries defined in values of device status parameters. The memory device is configured to receive a read command to read a memory block with a read address and identify a cluster for the memory block with the read address. The memory device is also configured to select a cluster read threshold for the identified cluster from the look-up table, and use the selected cluster read threshold to perform a read operation of the memory block.

Read threshold optimization in flash memories

Techniques for processing bits associated with an 'N' multiple level cell NAND flash memory, such as a QLC NAND flash memory, are described. In an example, a system generates a symbol based on the bits. The symbol corresponds to at least two bits. The system encodes the symbol in a non-binary codeword and stores the non-binary codeword in the 'N' multiple level cell NAND flash memory based on a mapping between symbols and voltage levels of the &#x201c;N&#x201d; multiple level cell NAND flash memory. The system initializes a non-binary decoding procedure based on asymmetric crossover probabilities between the voltage levels. The asymmetric crossover probabilities are defined based on the mapping between the symbols and the voltage level. The system decodes the non-binary codeword based on the non-binary decoding procedure.

Symbol-based coding for NAND flash devices

An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof.

Memory system of 3D NAND flash and operating method thereof

Techniques and systems are provided for copying, with or without error-fixing or corrections, data associated with a first set of locations to a second set of locations in a flash memory. Example methods disclosed, when performed by a flash memory controller, can significantly improve latency of operations. Embodiments of the disclosure can be used, for example, in a garbage collection process of a NAND flash memory.

Systems and methods for low latency copy operations in non-volatile memory

Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold.

Systems, methods and devices for limiting current consumption upon power-up

Growing community of inventors

San Jose, CA, United States of America

June Lee