Samsung Display Co., Ltd.

Jundal Kim

Jongman Bae

Kyungyoul Min

HyunSu Kim

Dong-Won Park

JunYong Song

Chaehee Park

Hyunsu Kim

Boram Shin

Hyunkyu Jo

Taeyoung Jin

Du-hyun Kim

Jaiho Kim

A transceiver includes a transmitter which transmits clock-embedded data through a line, where the clock-embedded data includes a clock training pattern, a start pattern, an encoded payload, and an end pattern, and a receiver which receives the clock-embedded data through the line, detects a clock embedding-related error from the clock-embedded data, and outputs an error flag corresponding to the clock embedding-related error to the transmitter.

Transceiver, method of driving the same, and display device

A transceiver includes a transmitter which transmits frame data through a first interface during a frame period including a vertical back porch period, a vertical active period, a vertical front porch period, and a variable vertical front porch period, and a receiver connected to the transmitter through the first interface and a second interface. The receiver transmits a start pulse of a synchronization signal to the transmitter through the second interface before starting transmission of the frame data. The transmitter transmits synchronization pulses of the synchronization signal to the receiver through the second interface during the variable vertical front porch period.

Transceiver, electronic device, and driver

A data transceiver system includes an encoder which generates first encoded data by performing a logical operation based on a random number and image data, and generates second encoded data by inverting the first encoded data every N bits, where N is a positive integer greater than or equal to 2, and a decoder which restores the first encoded data by decoding the second encoded data, and restores the image data by decoding the first encoded data.

Data transceiver system, display system, and display device

An electronic device includes a host processor including a data transmitter, a driving driver, and a display panel. The data transmitter includes a phase locked loop that generates a first clock and a second clock, a clock block that receives the first clock, a plurality of data blocks that receives the second clock, a first buffer connected between the phase locked loop and the clock block, and a plurality of second buffers respectively connected between the phase locked loop and the plurality of data blocks, and the first buffer and each of the plurality of second buffers may be activated or deactivated depending on an interface mode.

Processor and electronic device including the same

A display device includes a driving controller, a display panel, and an emission driver. The driving controller generates a second clock signal having second pulses in response to a first clock signal having first pulses from an external device. The display panel includes pixels. The emission driver generates an emission signal having third pulses in response to the second clock signal and applies the emission signal to the pixels. The driving controller compares a number of the first pulses and a number of the second pulses, with a first reference value, and a second reference value, and sets a compensation value of the number of the second pulses, and the driving controller compensates for the second clock signal by adjusting the number of the second pulses existing in one horizontal time based on the compensation value in a vertical blank period of the frame period.

Display device and method of driving the same

A host processor includes a high-speed driver which generates first high-speed data, a coupling circuit which receives the first high-speed data from the high-speed driver, and removes a direct-current ('DC') component of the first high-speed data to generate second high-speed data, a low-power driver which generates low-power data, and a passive switch which receives the second high-speed data from the coupling circuit, receives the low-power data from the low-power driver, and selectively outputs the second high-speed data or the low-power data to a display apparatus.

Host processor, display system including the host processor, and method of operating the display system

A voltage generating circuit includes: a first output voltage generator to receive an input voltage, to output a first output voltage, to compare the input voltage with a first reference voltage, and to stop the output of the first output voltage according to the comparison; and a second output voltage generator to receive the input voltage, to output a second output voltage, to compare the input voltage with a second reference voltage, and to stop the output of the second output voltage according to the comparison. The first output voltage generator is to compare first reference voltage data with second reference voltage data, and to change the first reference voltage according to the comparison. The second output voltage generator is to compare the first reference voltage data with the second reference voltage data, and to change the second reference voltage according to the comparison.

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Asan-si, South Korea

Jundal Kim