Photonic Technologies (shanghai) Co., Ltd.

Semiconductor Manufacturing International (shanghai) Corporation

Juncheng Wang

Xuefeng Chen

Rui Bai

Patrick Yin Chiang

Xin Wang

Tao Xia

Wenjun He

Shang Hu

Wenzong Pan

Zhichun Wang

Yuanxi Zhang

Zhigang Fu

Ming Lu

Jinzhong Peng

Jianxu Ma

Dongxiang Luo

Qinglong Lin

An apparatus comprises one or more non-clock and data recovery (CDR) components on a substrate, a signal generator on the substrate and coupled to at least one of the one or more non-CDR components, and a CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is configured to recover clock data from a received signal by the CDR component, and configured to determine a signal based on the received signal and the clock data.

Method and apparatus for built-in self-test of CDR and non-CDR components with an on substrate test signal generator

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Clock and data recovery circuit

Frequency detector, and clock and data recovery circuit including the frequency detector

Non-transitory machine readable medium for clock recovery

Apparatus and method for clock recovery based on non-non return to zero (non-NRZ) data signals

Frequency detector for clock recovery

Apparatus and method for clock recovery

The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval. The PLL, lock detector thereof and lock detection method can detect the lock state quickly and correctly.

Phase locked loop, lock detector and lock detection method

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Shanghai, China

Juncheng Wang