Xilinx, Inc.

Beijing Deephi Intelligent Technology Co., Ltd.

Junbin Wang

Shaoxia Fang

Yi Shan

Lingzhi Sui

Qian Yu

Xi Wang

Cheng Chen

Taobo Wang

Jiangsha Ma

Approaches for determining quantization scale factors include generating a population of chromosomes. Each chromosome has multiple genes, and each gene specifies a scale factor associated with a layer of a machine learning model. The population of chromosomes are evaluated, and the evaluating includes, for each chromosome in the population, quantizing floating point weights and floating point values of a representative dataset using the scale factors of the chromosome to produce quantized weights and a quantized dataset in the memory arrangement, initiating processing of the quantized dataset using the quantized weights according to the machine learning model, and gauging a level of accuracy of results produced by the processing of the quantized dataset. Satisfaction of termination criteria is determined based the levels of accuracy associated with the chromosomes in the population. The population of chromosomes is evolved and the evaluating repeated in response to the termination criteria not being satisfied.

Determining quantization scale factors for layers of a machine learning model

A high parallelism computing system and instruction scheduling method thereof are disclosed. The computing system comprises: an instruction reading and distribution module for reading a plurality of types of instructions in a specific order, and distributing the acquired instructions to corresponding function modules according to the types; an internal buffer for buffering data and instructions for performing computation; a plurality of function modules each of which sequentially executes instructions of the present type distributed by the instruction reading and distribution module and reads the data from the internal buffer; and wherein the specific order is obtained by topologically sorting the instructions according to a directed acyclic graph consisting of the types and dependency relationships. By reading the instructions based on the topological sorting the directed acyclic graph constructed according to the types and dependency relationships, the deadlock caused by the instruction dependencies can be avoided by a relatively simple operation.

High parallelism computing system and instruction scheduling method thereof

The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer module, a convolution operation unit and a hybrid computation unit. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.

Device for implementing artificial neural network with separate computation units

The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer pool, a data reading scheduling unit and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.

Device for implementing artificial neural network with flexible buffer pool structure

The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, a first instruction unit, a second instruction unit, an instruction distributing unit, a data transferring controller, a buffer module and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.

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Beijing, China

Junbin Wang