Yangtze Memory Technologies Co., Ltd.

Junbao Wang

Jianquan Jia

Yuanyuan Min

XiangNan Zhao

Ying Cui

Lei Jin

Ying Huang

Feng Xu

Chenhui Li

HongTao Liu

Wei Qi

The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Memory devices and operating methods thereof, memory systems

In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Method of improving program operation speed in 3D NAND systems

The embodiments of the disclosure provide a control method and apparatus for a memory, and a storage medium. The memory has memory blocks, and each memory block has memory strings. Each of the memory strings includes a channel layer with an N-type doped top region. In a memory block, a bit line erasing voltage is applied to a select bit line, and an erasing prohibition voltage is applied to an unselect bit line. A top select gate voltage lower than the bit line erasing voltage is applied to a top select gate. When a word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word line connected to a memory string corresponding to the select bit line and the unselect bit line, the memory string corresponding to the select bit line is erased.

Control method for memory erase operations, apparatus, and storage medium thereof

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Wuhan, China

Junbao Wang