Marvell International Limited

Synopsys, Inc.

Marvellworld Trade Ltd.

Paypal, Inc.

Ess Technology, Inc.

Vimicro Corporation

Jun Zhu

Joseph Jun Cao

Ian A Swarbrick

Sheng Lu

Pantas Sutardja

Samitinjoy Pal

Saswat Mishra

Akshay Chandra

Tsung-Ju Yang

Ruoyang Lu

Hongyan Liu

Can Ma

Peter Tze-Hwa Liu

Liping Guo

Srinivasan Manoharan

Vinesh Chirakkil

Harish Nalagandla

Yan Zhu

Christopher S Purdum

Sahil Dahiya

Girish Sharma

Gurinder Grewal

Akanksha Mehta

Ting Qu

Zhihua Chen

Weiping Fang

Sheng De Jang

Ofer Zaarur

Shawn Chen

Yuli Xue

Guoxin Li

Gokhan Gultoprak

Ke Fan

YunDong Zhang

Jian-Xun Yao

Sharanya Divakaruni

Yunyun Xiao

Paul C Liu

Biswanath Tayenjam

Toshinao Matsumura

Systems and methods for address mapping for a memory system are described. A system address that includes a first set of bits may be received. The first set of bits may be partitioned into at least a second set of bits and a third set of bits. A fourth set of bits may be determined based on the second set of bits. A memory address may be determined by using the third set of bits and the fourth set of bits.

Address mapping for a memory system

Disclosed is a configuration to store metadata using an error correction code (ECC). The configuration receives at an ECC encoder of a memory controller, write data and an N-bit metadata, N comprising an integer greater than 0. The configuration generates a meta symbol using the N-bit metadata and creates an enhanced write data, the enhanced write data comprising the write data and the meta symbol generated by the N-bit metadata. The configuration encodes the enhanced write data and meta symbol to generate a parity. It deletes the meta symbol to generate an output, the output comprising an enhanced codeword and writes the enhanced codeword to a memory.

Using multiple error correction code decoders to store extra data in a memory system

Methods and systems for using machine learning to automatically determine a data loading configuration for a computer-based rule engine are presented. The computer-based rule engine is configured to use rules to evaluate incoming transaction requests. Data of various data types may be required by the rule engine when evaluating the incoming transaction requests. The data loading configuration specifies pre-loading data associated with at least a first data type and lazy-loading data associated with at least a second data type. Statistical data such as use rates and loading times associated with the various data types may be supplied to a machine learning module to determine a particular loading configuration for the various data types. The computer-based rule engine then loads data according to the data loading configuration when evaluating a subsequent transaction request.

Self learning data loading optimization for a rule engine

A method for performing phase aware dynamic scheduling of a plurality of double data rate (DDR) commands includes determining a ratio of a frequency of DDR controller clock to a frequency of a DDR clock. The method includes determining a number of clock cycles of the DDR clock required for each DDR command of the plurality of DDR commands. The method includes, based on the ratio of the frequency of the DDR controller clock to the frequency of the DDR clock and the number of clock cycles of the DDR clock required for each DDR command, determining a sequence of the plurality of DDR commands according to a priority corresponding to the each DDR command, and transmitting the plurality of DDR commands to DDR devices over one or more clock cycles of the DDR controller clock according to the determined sequence of the plurality of DDR commands.

Phase-aware DDR command dynamic scheduling

A system and a method are disclosed for error correction during operations of a memory system. For example, during a read operation, the error correction includes a read retry determination to account for link errors that are detectable by cyclic redundancy check (CRC) but not correctable by error correction coding (ECC). Reducing the number of read retry operations performed may improve system performance by reducing the number of clock cycles spent on retry operations that could have otherwise been allocated for other system services (e.g., completing read and write operations). Additional CRC calculations and checks may be used to determine when to perform a retry in addition to existing CRC and ECC checks, reducing the number of potential retry operations and improving system performance.

Post-ECC CRC for DDR CRC retry performance improvement

Disclosed herein are system and electronic structure embodiments for implementing phase-aware control and scheduling. An embodiment includes a system with a bus controller configured to be activated in response to a first command. The bus controller may have a first clock speed and may drive an interface having a second clock speed. The system may further configure the bus controller to wait for a first time period in response to being activated, and a first circuit element structured to detect a first phase value of a first signal. In some embodiments, the bus controller may process a second command following passage of the first time period, and wait for a second time period, based on the detected first phase value and a ratio of the first and second clock speeds.

Phase-aware control and scheduling

A method includes, in at least one aspect, designating a first region of a memory device for storing data of a first type and first error correcting code (ECC) data; designating a second region for storing data of a second type and second ECC data; receiving the data of the first type; generating the first ECC data for the data of the first type using a first ECC associated with a first ECC protection level; storing the data of the first type and the first ECC data in adjacent locations of the first region; receiving the data of the second type; generating the second ECC data for the data of the second type using a second ECC associated with a second ECC protection level; and storing the data of the second type and the second ECC data in the second region.

Providing error correcting code (ECC) capability for memory

Systems, methods, and other embodiments associated with cyclic redundancy checking for wide data busses are described. According to one embodiment, a method comprises, in response to detecting a data block on a data bus, identifying a data lane of the data bus on which the data block begins and initializing a starting processing unit of a series of processing units. The starting processing unit corresponds with the identified data lane by issuing a mask input to prior processing units that are ahead of the starting processing unit within the series. Issuing the mask input causes the prior processing units to feed a seed value to the starting processing unit. A cyclic redundancy check value is generated for the data block by initiating the generating from the starting processing unit and iteratively cycling through the series of processing units until the block of data is completed.

Method and apparatus of feeding a seed value to a processing unit to initialize cyclic redundancy checking

A method includes, in at least one aspect, determining a relative delay of a signal path with respect to a timing budget; determining that the signal path is active; determining a value of a voltage being supplied to the signal path; and causing an adjustment in the voltage being supplied to the signal path based on the relative delay, the signal path being active, and the value of the voltage being supplied to the signal path.

Universal adaptive voltage scaling system

Apparatuses and techniques for dynamic credit control in the context of a multi-traffic class communication system are described. Dynamic credit control is provided through the use of central-controlled, traffic class receiver buffers for multiple traffic classes. The size of the traffic class receiver buffers can be modified on-the-fly, during operation of the system. This provides a high degree of flexibility, particularly in the context of heavy traffic class packet traffic which, in turn, greatly facilitates operation of today's advanced applications.

Dynamic credit control in multi-traffic class communication system

Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.

System and method of memory electrical repair

Systems and methods are provided for encoding forwarded error for data bus width conversion. Input data and input forwarded error information are received. System input parity information is computed based on the input data and the input forwarded error information. Output data based on the input data and system output parity information based on the system input parity information are provided, and it is determined whether to indicate a forwarded error output based on the output data and the system output parity information.

Systems and methods for handling parity and forwarded error in bus width conversion

Systems, methods, and other embodiments associated with providing dynamic switching between memory access modes are described. According to one embodiment, an apparatus includes first memory and second memory. The apparatus also includes a memory control logic configured to facilitate memory access of the first memory and the second memory using either a first memory access mode or a second memory access mode. The first memory access mode is configured to facilitate memory access of both the first memory and the second memory. The second memory access mode is configured to facilitate memory access of one of the first memory or the second memory. The memory control logic is configured to dynamically switch between the first memory access mode and the second memory access mode, without having to remap memory or reboot the system, in accordance with a region-based memory address mapping technique.

System and method for memory access dynamic mode switching

Growing community of inventors

San Jose, CA, United States of America

Jun Zhu