Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

Huazhong University of Science and Technology

Jun Zhou

Yun Li

Sheng Hu

Qiong Zhan

Peng Sun

Wei Huang

Chunyuan Hou

Bin Hu

Le Li

Kaiwei Cao

Qingwei Luo

Hu Yang

Chenglong Wu

Senhua Shi

Guangjie Xue

Qize Zhong

Junwen Zhong

Chaoran Zhang

Qiyi Hu

The present invention provides a large die, a method of forming the large die and a large die wafer. The method includes: providing a wafer containing a plurality of large dies each having a size greater than that of a maximum field of exposure of a stepper, each large die including at least two die portions to be stitched together, the die portions including a substrate and a first metal layer, the first metal layer including at least to-be-interconnected metal layers for interconnection of the die portions; and forming a second metal layer including at least inter-die interconnecting metal layers crossing dummy dicing margins between adjacent die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent die portions. The present invention allows interconnection of the die portions to be stitched together in each large die.

Large die wafer, large die and method of forming the same

Semiconductor structure, comprising a memory-array unit comprising: a substrate, a memory array disposed on the substrate, and a first bonding region disposed around the memory array. The memory array comprises multiple word lines, multiple bit lines, and multiple source lines. The first bonding region comprises a first substrate-connecting bonding region, a first bit-line bonding region, a first word-line bonding region, and a first source-line bonding region. The first substrate-connecting bonding region is configured to connect the substrate electrically to a surface of the memory-array unit, the first bit-line bonding region is configured to connect the bit lines electrically to the surface of the memory-array unit, the first word-line bonding region is configured to connect the word lines electrically to the surface of the memory-array unit, and the first source-line bonding region is configured to connect the source lines electrically to the surface of the memory-array unit.

Three dimensional semiconductor memory structure

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a device wafer and a carrier wafer, the device wafer including an SOI substrate comprising, stacked from the bottom upward, a lower substrate, a buried insulator layer and a semiconductor layer; bonding the device wafer at a front side thereof to the carrier wafer; removing at least the lower substrate through thinning the device wafer from a backside thereof, wherein the backside of the device wafer opposes the front side thereof; and providing a high-resistance substrate and bonding the device wafer at the backside thereof to the high-resistance substrate, the high-resistance substrate having a resistivity higher than that of the lower substrate. With the present disclosure, lower signal loss and improved signal linearity can be achieved while avoiding a significant cost increase.

Semiconductor device and method of fabricating the same

A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

Method of fabricating integrated circuit device

A floating gate fabrication method is disclosed. The method includes: providing a substrate, and depositing an oxide layer on the substrate; fabricating a shallow trench isolation in the substrate, a top surface of the shallow trench isolation being higher than a top surface of the oxide layer; depositing a polysilicon layer on the oxide layer and the shallow trench isolation; performing a first thermal annealing process on the polysilicon layer, thereby repairing cavities formed after the deposition of the polysilicon layer; implanting ions into the polysilicon layer; performing a second thermal annealing process on the polysilicon layer, thereby activating the implanted ions and repairing again the cavities formed after the deposition of the polysilicon layer; and planarizing the polysilicon layer to form a floating gate.

Floating gate fabrication method

A method for relieving a hole defect of a gate is disclosed, which includes: providing a substrate; forming a polysilicon layer over the substrate; forming a sacrificial oxide layer over a surface, that faces away from the substrate, of the polysilicon layer; forming a patterned photoresist layer over the sacrificial oxide layer; performing ion implantation by using the patterned photoresist layer as a mask; removing the patterned photoresist layer and the sacrificial oxide layer. In the method, before ion implantation, an oxide layer is formed over the surface of the gate, and is used to reduce affinity of the polysilicon and the photoresist layer. Afterwards, the floating gate is cleaned for many times, and hydrofluoric acid of an appropriate amount is added, so as to completely remove the photoresist layer and other residues while cleaning off the sacrificial oxide layer.

Gate hole defect relieving method

A method for alleviating an etching defect of a salicide barrier layer is disclosed. The salicide barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer. When the salicide barrier layer is being etched, the third barrier layer is removed during first etching. In this case, the second barrier layer is used as an etch stop layer, and the second barrier layer is removed during second etching. In this case, the first barrier layer is used as an etch stop layer, the first barrier layer is removed during third etching. The salicide barrier layer is divided into three layers, the second barrier layer and the first barrier layer are respectively used as an etch stop layer, so that the third barrier layer and the second barrier layer can be prevented from being over-etched, thereby effectively avoiding defects caused by over-etching and alleviating device performance.

Method for alleviating etching defect of salicide barrier layer

A paper-base flexible power-generation apparatus, and a manufacturing method thereof. The flexible power-generation apparatus comprises: a first assembly () formed by a paper-base insulation layer () and a first metal conductive layer () deposited on the surface of the paper-base insulation layer, and a second assembly () formed by a paper-base insulation layer (), a second metal conductive layer () deposited on the surface of the paper-base insulation layer, and an electret material layer () coating on the surface of the second metal conductive layer. The two edges of the two assemblies are each provided with an electrode () and the electrodes are connected through a packaging process. The first metal conductive layer is opposite to and spaced from the electret material layer. The flexible power-generation apparatus has a low cost, is easy to manufacture, has high output power, and is especially suitable for being integrated with other flexible electronic devices.

Growing community of inventors

Hubei, China

Jun Zhou