Amkor Technology, Inc.

Other

Jun Young Yang

Sean Timothy Crowley

Angel Orabuena Alvarez

Sang Ho Lee

Choon Heung Lee

Seon Goo Lee

Chul Woo Park

Won Sun Shin

Sun Goo Lee

Tae Hoan Jang

Won Dai Shin

Won Kyun Lee

Jong Hae Hyun

Chang Hoon Ko

A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor chip to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads defines a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spatial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.

Near chip size semiconductor package

An optic semiconductor package includes a main board of a substantially planar plate shape. The main board includes an aperture therethrough and a plurality of board metal patterns formed at the periphery of the aperture. A package portion is coupled to the main board. The package portion includes a base, a laser diode and a photo detector electrically coupled to the board metal patterns of the main board and bonded to the base. An optical fiber is inserted into the aperture of the main board and disposed adjacent the package portion. The position and tilt of the optical fiber may be adjusted to achieve optimum optical coupling between the optical fiber and the laser diode and the optical fiber and the photo detector. The optical fiber is stably attached to the main board by an adhesive.

Optic semiconductor module and manufacturing method

Leadframe-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

Stackable semiconductor package and method for manufacturing same

A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

Semiconductor package including passive elements and method of manufacture

A semiconductor package comprising a low temperature co-fired ceramic substrate defining opposed top and bottom surfaces. The substrate comprises at least two stacked ceramic layers and electrically conductive patterns which extend between the layers and along the top surface of the substrate. Mounted to the top surface of the substrate and electrically connected to the conductive patterns is at least one semiconductor die. A plurality of leads extend at least partially about the substrate in spaced relation thereto. Each of the leads defines opposed top and bottom surfaces, the semiconductor die being electrically connected to at least one of the leads. A package body at least partially encapsulates the substrate, the semiconductor die and the leads such that at least a portion of the bottom surface of each of the leads is exposed in the package body.

Semiconductor package including low temperature co-fired ceramic substrate

A stackable semiconductor package having a lead frame, a plurality of electrical paths, and a sealing material. The leadframe has a plurality of leads, each one of the plurality of leads having a top portion exposed to a top surface of the semiconductor package and a bottom portion resting flush with a bottom surface of the semiconductor package. In this manner, the leads extending from the top surface to the bottom surface of the semiconductor package provide an electrical path for connecting and electrically powering a second semiconductor package stacked on top of a first bottom semiconductor package.

An optic semiconductor package includes a plate shaped substrate having an insulation layer through which two spaced apart layer apertures are formed. The substrate further includes a plurality of electrically conductive patterns formed on the wall surfaces of the layer apertures and a lower surface of the insulation layer. One of a laser diode and a photo detector are disposed in a different one of the two layer apertures and are each electrically connected to the electrically conductive patterns through conductive bumps formed on the laser diode and the photo detector. An insulation plate, having a plurality of plate apertures formed through portions of the insulation plate adjacent to the electrically conductive patterns, is coupled to the lower surface of the substrate. One of a plurality of conductive pins electrically connected with the electrically conductive patterns is fitted in each of the plate apertures of the insulation plate and extends downward from the insulation plate. An integral metal cap is attached to upper and side portions of the substrate to protect the substrate, the laser diode, and the photo detector from the outside environment. The metal cap has an opening formed in its ceiling. A glass is attached below the opening to enable light to be transmitted through the glass from the laser diode to an exterior device and from an exterior device to the photo detector.

Optical structure having an optical diode and a sensor in separate apertures inside double insulating layers

A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads define a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spacial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.

Micro lead frame (MLF)-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

A circuit board for semiconductor package is designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges. The printed circuit board for semiconductor package includes: a resinous substrate; a chip mounting region formed on the top surface of the resinous substrate for mounting a semiconductor chip thereon; a plurality of fine circuit patterns radially disposed in the circumference of the chip mounting region and extending to the edge of the chip mounting region; a plurality of ball lands formed in an array on the bottom surface of the resinous substrate, to be fused to conductive balls; a conductive via hole connecting the circuit patterns on the top surface of the resinous substrate to the ball lands on the bottom surface of the resinous substrate; a cover coat applied to the top and bottom surfaces of the resinous substrate to protect the circuit patterns from an external environment and make the ball lands open to the exterior; and a means for removing electrostatic charges provided at the edge of the substrate and connected to the plural circuit patterns to remove electrostatic charges in the manufacture of semiconductors.

Growing community of inventors

Seoul, South Korea

Jun Young Yang