Samsung Electronics Co., Ltd.

Soulbrain Co., Ltd.

Jun-Youl Yang

Kyunghyun Kim

Se-Ho Cha

Daehong Eom

Byoung-Moon Yoon

Kihyun Hwang

JinGyun Kim

Yongsun Ko

Kijong Park

Daehyun Jang

Sunghae Lee

Taeheon Kim

Kwangsu Kim

Chadong Yeo

Seongsoo Lee

Jae Jin Shin

Hoon Hee Han

Won-Jun Lee

Seung-Ho Park

Joon-Sang Park

Jae-Wan Park

Jin-Uk Lee

Ki-Hyung Ko

Young-taek Hong

Young-Ok Kim

Kyung-hyun Kim

Tae-Heon Kim

Jung-hun Lim

Myung-Jung Pyo

Keon-Young Kim

Dae-hong Eom

Sun-Joong Song

A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

Method and apparatus for plasma etching

Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

Methods of fabricating three-dimensional semiconductor devices

The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.

Methods of forming conductive patterns and methods of manufacturing semiconductor devices using the same using an etchant composition that includes phosphoric acid, nitric acid, and an assistant oxidant

Three dimensional semiconductor memory devices and methods of fabricating the same

According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.

Non-volatile memory device having vertical structure and method of manufacturing the same

A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.

Vertical channel memory devices with nonuniform gate electrodes and methods of fabricating the same

Vertical channel memory devices with nonuniform gate electrodes

In an etching method, a thin layer is formed on a first surface of a first substrate doped with first impurities having a first doping concentration. The thin layer is doped with second impurities having a second doping concentration lower than the first doping concentration. A second substrate is formed on the thin layer. A second surface of the first substrate is polished. The polished first substrate is cleaned using a cleaning solution including ammonia and deionized water. The cleaned first substrate is etched to expose the thin layer.

Etching methods and methods of manufacturing a CMOS image sensor using the same

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Seoul, South Korea

Jun-Youl Yang