Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Jun-yong Park

Dae-Yong Kim

Soo-hyun Whang

Jee-hoon Park

Sang-Won Hwang

You-na Choo

Hyun-yong Choi

Su-Bin Song

Kyoung-Doo Kang

Ha-Na Kim

Won-Ju Yi

Seok-Gyun Woo

Il-Han Park

Jong-Hoon Lee

Bo-Geun Kim

Byung-Soo Kim

Min Hur

Young-Do Choi

Chong-Gi Hong

Hyun-suk Kim

Takahisa Mizuta

Donghyeon Kim

Soo-Hong Kim

Jae-Yun Lee

Dong-hun Shin

Young-ah Lee

Mun-Ho Nam

Woong-ki Lee

Young-mo Kang

Dae-wung Kim

Su-won Shin

Sung-jun Hwang

Sung-do Son

Seok-ho Ban

An electronic device that is interlocked with a display device and a method for controlling the electronic device are provided. The method includes acquiring an image by photographing an area in which the display device is installed, identifying a display area in which the display device is disposed and a background area of the display device by analyzing the acquired image, acquiring information that relates to a background image of a position at which the display device is installed based on the identified background area, and transmitting the acquired background image information to the display device.

Electronic device and method for controlling the same

An electronic apparatus includes a communicator, an image capturer configured to acquire a capture image of a display apparatus including a screen, and a processor configured to identify a screen area of the screen, within the capture image. The processor is further configured to sample a plurality of patch images, each of which having a predetermined unit size, from a background area outside the screen area within the capture image, generate a screen image to be displayed on the screen, based on the plurality of patch images, and control the communicator to transmit the screen image to the display apparatus.

Electronic apparatus for generating screen image to be displayed by display apparatus and control method thereof

A display apparatus, including a display configured to display an image, at least one sensor configured to generate sensing data relating to at least one from among a direction and an intensity of external light projected onto the display from an external light source disposed around the display, a memory configured to store background image data relating to a background image of a background area behind the display, and a processor configured to generate a content screen based on the background image data and the sensing data and control the display to display the content screen, wherein the content screen may include at least one graphic object and a shadow corresponding to the at least one graphic object disposed on the background image, and at least one of a position and a shade of the shadow is changed in response to a change in the sensing data.

Display apparatus and method of controlling the same

A display apparatus, including a display configured to display an image, at least one sensor configured to generate sensing data relating to a position of a user with respect to the display apparatus, a memory configured to store background image data relating to a background image of a background area behind the display, and a processor configured to generate a content screen based on the background image data and the sensing data and control the display to display generated content screen, wherein the content screen includes at least one graphic object disposed on the background image, and wherein at least one from among the background image and the at least one graphic object are changed in response to a change of the sensing data.

Display apparatus and method for controlling the display apparatus

Provided is a nonvolatile memory device and an operating method thereof. The operating method for programming a first memory block from among a plurality of memory blocks includes: programming a first word line connected to the first memory block by sequentially executing first to N(N is a natural number) programming loops; applying a voltage generated by regulating a first pump voltage of a first charge pump to the first word line as a dummy verifying voltage after the programming is completed; generating a first detection count based on the first pump voltage and a first reference voltage; and outputting a bad block setting signal for setting the first memory block as a bad block based on a result of comparing the first detection count with the first reference count.

Nonvolatile memory device and operating method thereof

A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.

Flash memory device and a method of programming the same

In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Non-volatile memory device and method of operation therefor

A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.

Flash memory device and method of testing the flash memory device

A plasma display panel (PDP) with improved address voltage margin and reduced noise brightness such as discharge light or background light during an address discharge. The PDP includes a plurality of barrier ribs between a front substrate and a rear substrate to define a plurality of main discharge spaces and a plurality of auxiliary discharge spaces along a stepped surface of the barrier ribs. The auxiliary discharge spaces provide a shorter discharge path than the main discharge spaces. Address electrodes are provided on the rear substrate for generating address discharges together with the scan electrodes on the front substrate at locations adjacent to the auxiliary discharge spaces. Phosphor layers are respectively formed in the main discharge spaces, and a discharge gas is injected in the main discharge spaces and the auxiliary discharge spaces.

Plasma display panel

In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.

A plasma display panel comprises: first and second substrates facing each other; a plurality of barrier ribs partitioning a discharge space between the first and second substrates so as to define a plurality of discharge cells; address electrodes extending in parallel with each other and in a predetermined direction; first and second electrodes disposed on the second substrate in a direction intersecting the direction of the address electrodes, the first and second electrodes being separated from the address electrodes, the first and second electrodes being provided in correspondence with each of the discharge cells; and phosphor layers coated on the discharge cells. The first and second electrodes protrude in a direction from the second substrate to the first substrate, and face each other so as to provide a space therebetween.

Plasma display panel provided with dielectric layer having a variation in thickness in relation to surfaces of a display electrode

A Plasma Display Panel (PDP) has a high aperture ratio of a discharge cell, a high light transmittance, and a high luminous efficiency and a stable and efficient discharge occurs uniformly at a low driving voltage on inner sidewalls of the discharge cell and concentrates in the center of the discharge cell. The PDP includes: a front substrate and a rear substrate facing each other and separated from each other; barrier ribs of a dielectric material arranged between the front substrate and the rear substrate to define discharge cells together with the front substrate and the rear substrate; discharge electrodes arranged within the barrier ribs, the discharge electrodes being separated from each other and surrounding the discharge cells and having at least one corner portion for surrounding the discharge cells; fluorescent layers arranged in the discharge cells; a discharge gas contained within the discharge cells; and an attenuator adapted to reduce a strength of an electric field generated between at least one pair of corner portions of the discharge electrodes, the corner portions facing each other, to be less than a strength of an electric field generated between portions of the discharge electrodes facing each other, other than the corner portions, in the discharge cells.

Plasma display panel (PDP)

A Plasma Display Panel (PDP) includes: a front panel; a rear panel parallel to and separated from a front panel; a plurality of first barrier ribs of a dielectric, arranged between the front panel and the rear panel, and adapted to define discharge cells together with the front panel and the rear panel; front discharge electrodes and rear discharge electrodes disposed apart to surround each discharge cell within the first barrier ribs, each of the front discharge electrodes and rear discharge electrodes including main line parts and corner parts adapted to connect the adjacent main line parts, wherein inner surfaces of the corner parts facing each discharge cell, are rounded; a phosphor layer arranged in each discharge cell defined by the first barrier ribs; and a discharge gas filling each discharge cell.

Growing community of inventors

Suwon-si, South Korea

Jun-yong Park