Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kia Corporation

Dongwoo Hst Co., Ltd.

Jun Yong Park

Jin Kyeom Cho

Ha Na Kim

Dong Hyun Kim

Jun-Sang Lyu

Ho-Seok Han

Ho Seok Han

Hyun Gu Kim

Sang Wan Nam

Jung No Im

Yong Hyuk Choi

Sung Deok Kim

Hyun Yong Choi

Gyu Sung Do

Sun Young Park

Won Ki Chung

Soo Jin Chung

You Na Choo

Hyeon Seung Lee

Soo Hyun Whang

Young Min Shin

Jee Hoon Park

Sung Jun Hwang

Dae Wung Kim

Dong Hun Shin

Seok Ho Ban

Young Ah Lee

The present disclosure relates to a cooling device for heat treatment that performs heat treatment by cooling individually or as a whole a heated metal object. The cooling device for heat treatment includes: a chamber to which a plurality of objects is charged through one open side thereof; an individual cooling unit configured to be provided in the chamber, to individually cover the object, and to spray a cooling medium onto the object; and a driving unit configured to be provided on the chamber and to move the individual cooling unit in an up and down direction. With this configuration, it is possible to obtain a required cooling capacity by cooling individually or as a whole a heated metal object.

Cooling device for heat treatment

A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.The present disclosure provides a memory device for detecting a word line bridge defect through erase verification of the memory device. The memory device comprises: a first memory cell and a second memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; an address decoder which is configured to apply one of an erase voltage and an inhibit voltage to each of the first and second word lines; and a control logic which is configured to control an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

Memory device configured to alternately apply an erase voltage and an inhibit voltage

Proposed is an apparatus, software program, and a corresponding method of controlling driving of an electrified vehicle. The method includes increasing a level of regenerative braking on the basis of a remaining distance from the vehicle to a stop-event point when a brake control mode is entered, determining whether or not braking needs to be performed, on the basis of a stop approval signal when the remaining distance is equal to or less than a preset first distance in the brake control mode, and decreasing the level of regenerative braking when a distance of traveling of the vehicle from the stop-event point is equal or greater than a preset second distance in the brake control mode.

Electrified vehicle and method of controlling driving of same

Display module

Display panel

A display device includes: a host which transmits a first signal through a first interface, and transmits a second signal through a second interface different from the first interface; a display driver integrated circuit including a first interface unit which receives the first signal through the first interface, and a second interface unit which receives the second signal through the second interface; and a display panel which receives a data signal corresponding to the first signal and the second signal from the display driver integrated circuit, and displays an image.

Display driver integrated circuit and display device including the same

Systems and methods are described for a display driver integrated circuit that is configured to certify whether an application processor and the display driver integrated circuit are genuine products. The display driver integrated circuit includes: an encryptor for generating first encrypted data by encrypting first data; a data converter for converting the first data into a first converted signal expressed with four or more voltage levels; an interface for providing the first converted signal to a host processor, and receiving, from the host processor, a second converted signal corresponding to second encrypted data generated by the host processor; and a determiner for controlling a display panel by comparing the first encrypted data with converted data corresponding to the second encrypted data. The second converted signal transferred through the interface is expressed with the voltage levels.

Display driver integrated circuit and display system having the same

An electronic device includes: a host configured to output image data and a timing control signal in response to an image intended to be displayed; a display driver IC coupled to the host through a first interface and a second interface and configured to output a data signal based on the image data; and a display configured to display an image based on the data signal, wherein the host is configured to output the image data and the timing control signal through any one of the first interface and the second interface depending on a display mode.

Electronic device having multiple interfaces and method of driving the same

A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

Memory device and a storage system using the same

Growing community of inventors

Seoul, South Korea

Jun Yong Park