National Yang Ming Chiao Tung University

Jun-Yi Li

Yi-Bing Lin

Shie-Yuan Wang

Chia-Ming Wu

The present disclosure provides packet aggregation and disaggregation methods. In the packet aggregation methods, the protocol-independent packet processor (P) switch stores plural message headers of plural packets in the ring buffer. When the plural message headers stored in the ring buffer reach a pre-defined amount of data, the Pswitch replaces the first flag header in the current packet with a second flag header so as to form a work packet. The egress pipeline of the Pswitch recirculates the work packet repeatedly, whenever it receives a work packet, a message header is extracted from a plurality of message headers in the ring buffer and added to the working packet for packet aggregation.

Packet aggregation and disaggregation method

A high-speed data-plane packet aggregation and disaggregation method is disclosed. The method includes following steps: receiving a plurality of packets by the P4 switch; parsing each of the plurality of packets by using a parse graph; determining the type of the packets by using a match-action table; conducting packet aggregation and disaggregation process at the pipeline of the P4 switch; and transmitting the aggregated packet or the original data packet to a deparser of the P4 switch and outputting the aggregated packet or the original data packet by the P4 switch.

Growing community of inventors

Kaohsiung, Taiwan

Jun-Yi Li