Agency for Science, Technology and Research

Intel Corporation

Jun Ye Zhou

Xin Liu

Ingo Volkening

Minkyu Je

Tao Wang

Chao Wang

Anant Raj Gupta

Jung Hyup Lee

Vishal Vinayak Kulkarni

A set of data entries is transferred via a memory mapped interface from an external peripheral device to a processor device and is stored in a shared memory region. Based on a first pointer to the shared memory region, a first process executed by the processor device processes a first group of the data entries. Based on a second pointer to the shared memory region, a second process executed by the processor device processes a second group of the data entries. The second process indicates the second pointer to the first process. The first process indicates a lower one of the first pointer and the second pointer to the peripheral device.

Dual first and second pointer for memory mapped interface communication with lower indicating process

A method for detecting and correcting an error in a circuit is provided. The circuit is configured to receive an input signal and clock the input signal with a rising and falling timing signal. The method includes detecting late arrival signal transition of the input signal, at an intermediate point of a path, the path being one through which the input signal transits. The method further includes predicting an error in the input signal in response to detecting the late arrival signal transition at the intermediate point of the path. In addition, the method includes correcting the error in the input signal by manipulating the timing signal and/or a supply voltage.

Detecting and correcting an error in a digital circuit

An electrocardiogram (ECG) signal processing system is provided. The ECG signal processing system comprises an analog-to-digital converter (ADC) configured to convert an input analog ECG signal into a digital ECG signal, and a digital signal processing engine (DSPE) coupled to the ADC to receive the digital ECG signal. The DSPE is configured to decompose and reconstruct the digital ECG signal. A dynamic system clock source is coupled to the ADC and the DSPE for dynamic signal sampling, the dynamic system clock source clocking the ADC and the DSPE at a first frequency fto detect one or more first parameters of the input analog ECG signal and at a second frequency fto detect one or more second parameters of the input analog ECG signal.

Real-time multi-functional ECG signal processing system, DSPE for the ECG signal processing system, and method thereof

In various embodiments of the present disclosure, there is provided a receiver for body channel communication. The receiver includes an electrode configured to receive an incoming signal transmitted as a multi-level transmission signal from a transmitter through a body channel, a differentiator configured to obtain a time derivative of the incoming signal indicating a plurality of data transitions, and an analog to digital converter configured to generate a multi-level output signal representing the multi-level transmission signal based on the plurality of data transitions. A corresponding method of controlling a receiver for body channel communications is provided.

Receiver for body channel communication and a method of operating a receiver therefrom

A circuit arrangement may be provided including a level shifting stage configured to be coupled to a first reference voltage and a second reference voltage. The circuit arrangement may also include a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage and a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage. The level shifting stage may be configured to generate an output voltage above a predetermined output level at the output node due to the first reference voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state. The circuit arrangement may also include a feedback circuit coupled to the output stage and the level shifting stage and a voltage stabilization circuit coupled to the level shifting stage.

Circuit arrangement and method of operating the same

In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

Growing community of inventors

Singapore, Singapore

Jun Ye Zhou