Rambus Inc.

Other

Jun Y Kim

Donald C Stark

Wayne S Richardson

Mark A Horowitz

Kevin S Donnelly

Bruno Werner Garlepp

Pak Shing Chau

Jared L Zerbe

Scott C Best

Leung Yu

Stefanos Sidiropoulos

Roxanne T Vu

Tsyr-Chyang Ho

Benedict Chung-Kwong Lau

Kurt T Knorpp

Glenn Chiu

Thomas H Lee

Natsuki Kushiyama

Michael Tak-Kei Ching

Yiu-Fai Chan

Benedict C Lau

Yohan Usthavia Frans

Mark G Johnson

Simon Li

Chanh Vi Tran

Nhat M Nguyen

Michael T Ching

John Eric Linstadt

Steven Cameron Woo

Carl William Werner

Chad A Bellows

Haw-Jyh Liaw

Clemenz L Portmann

Eric Linstadt

In-Nan Wu

Eric Lindstadt

Kevin S Donelly

Jared Levan Zerbe

Horowitz Mark A A

H J Liaw

Park Chau

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Drift detection in timing signal forwarded from memory controller to memory device

A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Synchronous wired-or ACK status for memory with variable write latency

A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

Communication channel calibration using feedback

Synchronous wired-OR ACK status for memory with variable write latency

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Flash memory controller with calibrated data communication

Memory controller that calibrates a transmit timing offset

Drift adjustment in timing signal forwarded from memory controller to memory device based on a detected phase delay occurring on a second timing signal with a different frequency

Growing community of inventors

Baltimore, MD, United States of America

Jun Y Kim