Applied Materials, Inc.

Lam Research Corporation

Jun Xue

Ludovic Godet

Srinivas D Nemani

Ellie Y Yieh

Samantha S H Tan

Chentsau Chris Ying

Erica Chen

Yongmei Chen

Da Li

Mary Anne Manumpil

Jengyi Yu

Matthew D Scotney-Castle

Jingjing Liu

Qiwei Liang

Samantha SiamHwa Tan

Shih-Ked Lee

Christopher S Ngai

Martin A Hilkene

Gary E Dickerson

Nitin K Ingle

Abhijit Basu Mallick

Anchuan Wang

Michael Wayne Stowell, Jr

Eric A Hudson

Pramit Manna

Patrick A Van Cleemput

Mukund Srinivasan

Douglas Buchberger

Zihui Li

Prashanth Kothnur

Umesh M Kelkar

Ching-Mei Hsu

Shambhu Nath Roy

Nader Shamma

Daniel Peter

Alexander Kabansky

Matthew Scott Weimer

Younghee Lee

Mohand Brouri

Ragesh Puthenkovilakam

Yuanhui Li

Chin-Jui Hsu

Gordon Alex Macdonald

Shaoqing Zhang

Xizhu Zhao

Hongxiang Zhao

Ji Yeon Kim

Michelle Margarita Flores Espinosa

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an Oflash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

Integration of dry development and etch processes for EUV patterning in a single process chamber

This disclosure relates generally to a patterning structure including an underlayer and an imaging layer, as well as methods and apparatuses thereof. In particular embodiments, the underlayer provides an increase in radiation absorptivity and/or patterning performance of the imaging layer.

Underlayer for photoresist adhesion and dose reduction

Provided herein are methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate in a low pressure chamber using a dual frequency radio frequency component. Low pressure plasma enhanced chemical vapor deposition may be used to increase the etch selectivity of the AHM, permitting the use of a thinner AHM for semiconductor processing operations.

High density, modulus, and hardness amorphous carbon films at low pressure

A method for depositing a carbon ashable hard mask layer on a substrate includes a) arranging a substrate in a processing chamber; b) setting chamber pressure in a predetermined pressure range; c) setting a substrate temperature in a predetermined temperature range from −20° C. to 200° C.; d) supplying a gas mixture including hydrocarbon precursor and one or more other gases; and e) striking plasma by supplying RF plasma power for a first predetermined period to deposit a carbon ashable hard mask layer on the substrate.

High etch selectivity, low stress ashable carbon hard mask

A method for selectively etching layers of a first material with respect to layers of a second material in a stack is provided. The layers of the first material are partially etched with respect to the layers of the second material. A deposition layer is selectively deposited on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions covering the layers of the first material, the selective depositing comprising providing a first reactant, purging some of the first reactant, wherein some undeposited first reactant is not purged, and providing a second reactant, wherein the undeposited first reactant combines with the second reactant and selectively deposits on the layers of the second material with respect to the layers of the first material. The layers of the first material are selectively etched with respect to the layers of the second material.

Selectively etching for nanowires

Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall.

Material deposition for high aspect ratio structures

Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate disposed in a processing chamber includes: (a) depositing a layer of material on a substrate by exposing the substrate to a first reactive species generated from a remote plasma source and to a first precursor, wherein the first reactive species reacts with the first precursor; and (b) treating all, or substantially all, of the deposited layer of material by exposing the substrate to a plasma generated within the processing chamber from a second plasma source; wherein at least one of the remote plasma source or the second plasma source is pulsed to control periods of depositing and periods of treating.

Pulsed plasma for film deposition

A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Nanocrystalline diamond carbon film for 3D NAND hardmask application

Embodiments described herein relate to methods for forming flowable chemical vapor deposition (FCVD) films suitable for high aspect ratio gap fill applications. Various process flows described include ion implantation processes utilized to treat a deposited FCVD film to improve dielectric film density and material composition. Ion implantation processes, curing processes, and annealing processes may be utilized in various sequence combinations to form dielectric films having improved densities at temperatures within the thermal budget of device materials. Improved film quality characteristics include reduced film stress and reduced film shrinkage when compared to conventional FCVD film formation processes.

Advanced process flow for high quality FCVD films

Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

3D material modification for advanced processing

Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.

Air gap formation in interconnection structure by implantation process

Growing community of inventors

San Jose, CA, United States of America

Jun Xue