Sony Corporation

Marvell International Limited

Future Wei Technologies, Inc.

Micron Technology Incorporated

Velos Media, LLC

Cisco Technology, Inc.

Sony Group Corporation

Zenlayer Innovation LLC

Apple Inc.

Google Inc.

Futurewei Technologies Co., Ltd.

Jun Xu

Ali Jezu Tabatabai

Ehsan Maani

Gregory Burd

Zining Wu

Tony Yoon

Siu-Hung Fred Au

Ichiro Kikuchi

Kazushi Sato

Ohji Nakagami

Panu Chaichanavong

Heng Tang

Aditya Ramamoorthy

Adina Matache

Shaohua Yang

Cheung Auyeung

Engling Yeo

Henri Sutioso

Eugene Pan

Rangaraju Iyengar

Shree N Murthy

Xiangrong Wang

Ravi Shanker Chuppala

Seagle Yang

Hsi-Jung Wu

Teruhiko Suzuki

Violante Moschiano

Yeping Su

Xiaosong Zhou

Chris Yoochang Chung

Jun Xin

Mei Guo

Erwin E Yu

Massimo Rossini

Christopher H Pham

Guang Zhao

Huanyou Zhan

Theodore T Pekny

Paul Haahr

Trevor D Strohman

Chen Li

Manikam Muthiah

Gabriel Schine

Feng Yi

Adam Sadovsky

Jay Shrauner

Jingteng Xue

Per Bjornsson

Kitae Park

Huiyang Yang

Gopinath Palani

Sheng Xu

Srinivas Goli

An Ho

Dong Wang

Chandra Sekhar Putha

Hao Wang

Video coding systems or apparatus utilizing context-based adaptive binary arithmetic coding (CABAC) during encoding and/or decoding, are configured according to the invention with an enhanced binarization of non-zero Delta-QP (dQP). During binarization the value of dQP and the sign are separately encoded using unary coding and then combined into a binary string which also contains the dQP non-zero flag. This invention capitalizes on the statistical symmetry of positive and negative values of dQP and results in saving bits and thus a higher coding efficiency.

Binarization of dQP using Separate Absolute Value and Sign (SAVS) in CABAC

Methods and systems are disclosed to aggregate traffic from multiple server devices through a peripheral component interconnect (PCI) hosting device. In one embodiment, the PCI hosting device comprises a network interface to couple the PCI hosting device to a network, a plurality of PCI interfaces, a processing circuit to forward packets, and a power supply to supply power to the PCI interfaces independently from the plurality of server devices. Each of the PCI interfaces is designed to be coupled to one server device to the PCI hosting device, which is registered as a first PCI board of a first server device through a first PCI interface and as a second PCI board of a second server device through a second PCI interface, and the PCI hosting device is designed to forward packets between the network interface and the first server device, and the network interface and the second server device.

Peripheral component interconnect (PCI) hosting device

Methods and systems are disclosed to serve client requests in a communication network. In one embodiment, a method may be performed by a controller device to form a first consensus with a first plurality of controller devices to determine a role for the controller device. Upon the controller device being elected as a first single lead controller for the first consensus, the controller device packs a client request with other client requests into a block, validates the packed client requests within the block with the first plurality of controller devices, and seals the block after the packed client requests are validated. The controller device then forms a second consensus with a second plurality of controller devices, the second consensus electing a second single lead controller, the second single lead controller identifying one or more resources to serve the packed client requests in the sealed block.

Method and apparatus to coordinate multiple controller devices to serve client requests

A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

Defect detection during erase operations

A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

Charge loss detection using a multiple sampling scheme

A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.

Managing programming convergence associated with memory cells of a memory sub-system

Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes one or more programming pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective programming levels of a plurality of programming levels as part of the program operation. Responsive to the one or more programming pulses being applied, the control logic further performs a program verify operation to verify whether the memory cell in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.

All levels dynamic start voltage programming of a memory device in a memory sub-system

Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.

Memory cell sensing

Binarization of dQP using separate absolute value and sign (SAVS) in CABAC

Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

Estimating resistance-capacitance time constant of electrical circuit

An extension to the motion-constrained tile sets SEI message provides functionality to signal all tiles are independently decodable and to signal the ROIs that may have more than one tile per ROI. With this extension, the functionality to redefine any independently decodable region-of-interest in a CVS at a coding tree unit level based on user interactivity is enabled. The extension supports the interactivity utilized in various applications such as interactive Ultra High Definition Television (UHDTV), dynamic high-quality zoom-in application, interactive on-demand, e-learning, smart surveillance and many other applications. Additionally, the temporal MCTS SEI message is able to be used by an encoder for tiled streaming to signal explicitly to the decoder that the decoder need only to display the ROI.

Extensions of motion-constrained tile sets SEI message for interactivity

A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.

The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Chroma quantization parameter extension

A method and apparatus of using logical mode numbers during both prediction and coding in the bit stream, such as for high efficiency video coders (HEVC). These logical intra mode numbers are sorted based on angle which as a result leads to improved coding designs with fewer and smaller look-up tables, and a small gain in coding efficiency. Furthermore, by using this type of naming, the number of most probable modes (MPMs) can be readily extended since no additional tables are required. The use of three MPMs achieves a larger gain of 0.25% and 0.31% for the AI_HE and AI_LC cases, respectively.

Logical intra mode naming in HEVC video coding

Growing community of inventors

Sunnyvale, CA, United States of America

Jun Xu