Montage Lz Technologies (chengdu) Co., Ltd.

University of Electronic Science and Technology of China

Jun Xu

Mingfu Shi

Shunfang Wu

Xinwu Cai

Shen Feng

Taibo Dong

Bo Zhang

Zhuo Wang

Xin Ming

Tiansheng Li

Shawn Si

The present disclosure provides a multi-phase clock signal phase difference detection and calculation circuit and method, and a digital phase modulation system. The detection and calculation circuit includes an auxiliary digital-to-time conversion circuit, a main digital-to-time conversion circuit, a phase detector, and a state machine. The auxiliary digital-to-time conversion circuit selects a first phase clock signal and outputs an auxiliary clock signal, adjusts the phase of the auxiliary clock signal; the phase detector detects the phases of the auxiliary clock signal and a target clock signal output by the main digital-to-time conversion circuit; the state machine adjusts the phase of the auxiliary clock signal, and adjusts the phase of the target clock signal. When the phase difference between the two signals is zero, the amount of phase adjustment by the main digital-to-time conversion circuit is the phase difference between the first phase clock signal and the second phase clock signal.

Multi-phase clock signal phase difference detection and calculation circuit and method and digital phase modulation system

The present disclosure provides multi-channel receiver and multi-channel reception method. The method includes: amplifying an input RF signal and outputting differential RF signals; mixing multi-phase local oscillator signals with the received differential RF signals to generate differential multi-phase intermediate frequency signals; configuring weight coefficients for the differential multi-phase intermediate frequency signals; configuring the weight coefficients to be positive or negative according to a channel for reception corresponding to a harmonic of any order of the local oscillator signals; superimposing the signals processed by the weight coefficient configuration and the positive/negative configuration of the weights to simultaneously select an intermediate frequency signal downconverted by a harmonic of any order of the local oscillator signals and suppress intermediate frequency signals downconverted by harmonics of the other orders of the local oscillator signals; and receiving, by a channel reception module corresponding to each channel, a selected intermediate frequency signal corresponding thereto respectively.

Multi-channel receiver and multi-channel reception method

A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Low noise amplifier

The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Linear calibration system and method for time-to-digital converter and digital phase-locked loop

A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.

Radio frequency signal transceiver

A low-dropout regulator, including: a dynamic pole tracking circuit having an active load, a voltage-to-current converter, a current amplifier, a bias circuit, a regulating transistor, a first feedback resistor, a second feedback resistor, and a first capacitor. The dynamic pole tracking circuit includes: a first PMOS, a second PMOS, a first resistor, and a second resistor. The voltage-to-current converter includes: a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a third PMOS, a fourth PMOS, a seventh PMOS, an eighth PMOS. The current amplifier includes: a fifth PMOS, a sixth PMOS, a ninth NMOS, a tenth NMOS, and a third resistor. The bias circuit includes: a ninth PMOS, a tenth PMOS, an eleventh PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, and a fourth resistor.

Growing community of inventors

Chengdu, China

Jun Xu