Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Chinese Academy of Sciences

General Electric Company

Jun Xiao

Mingyong Huang

Hui Li

Hong Jiang

Weiran Kong

Binghan Li

Jing Li

Yunfeng Sun

Brian David Yanoff

Wenqing Peng

Yi Xu

Ping Hu

Xin Fu

Guangjun Yang

Liping Zheng

Jian Hu

Zhaoping Wu

Kun Tao

Wenyi Zhu

Li Deng

Maoyong He

Yuanyuan Cheng

Jiaxin Luo

Zhangdong Jin

Qing Zhou

A horizontal sampling soil drilling rig and a control method are used to solve the problem that the soil sampling device in the prior art has difficulty in horizontal sampling. The horizontal sampling soil drilling rig includes a rack, a connection assembly, a drive mechanism, a spiral drill rod, and a sampler. The rack is provided with a spline shaft and a screw rod in parallel. The screw rod and the spline shaft are connected through a first transmission assembly in transmission connection. The drive mechanism includes a rotation driver, a second transmission assembly, and a spline shaft sleeve. The spline shaft sleeve is rotationally connected to the rack, and the spline shaft sleeve and the spline shaft mesh with each other. The rotation driver is connected with the spline shaft through the second transmission assembly in transmission connection.

Horizontal sampling soil drilling rig and control method thereof

The application relates to a data reading circuit of an embedded flash memory cell. The data reading circuit a switch circuit, a current clamp circuit, a current mirror circuit, a reference current source, a precharge circuit and a comparison circuit; the switch circuit includes a transmission gate, one end of the transmission gate is connected with a drain of the embedded flash memory cell, and the other end of the transmission gate is connected with a detection end of the current clamp circuit; a response end of the current clamp circuit is connected with a data node; the current mirror circuit is connected with the reference current source and the data node; an output end of the precharge circuit is connected with the data node; one input end of the comparison circuit is connected with the data node, and the other input end is connected with reference voltage.

Data reading circuit of embedded flash memory cell

A charge pump control circuit is provided in embodiments of the present disclosure, and the charge pump control circuit includes: a charge pump, having a clock interface; a feedback circuit, configured to sample an output voltage of the charge pump to obtain a sampling voltage; a reference voltage generating circuit, having an output terminal outputting a reference voltage; and a comparator, configured to compare the sampling voltage with the reference voltage; wherein the charge pump control circuit further includes: a logic combination circuit, wherein an input terminal of the logic combination circuit is coupled with an output terminal of the comparator, and the logic combination circuit is configured to generate a clock pulse signal according to a comparison result outputted by the comparator, and the clock pulse signal is transmitted to the clock interface of the charge pump.

Charge pump control circuit

Provided is a muscle stem cell in vitro culture method. A muscle stem cell is cultivated in vitro by using a cell culture medium of a cell factor added with a blood cell or a conditioned medium of the blood cell. Also provided is a culture medium used in the muscle stem cell in vitro culture method and an application thereof.

Muscle stem cell in vitro culture method and application

A circuit for control of time for read operation is disclosed which additionally incorporates a dummy device circuit and a dummy sensitive amplifier circuit, uses a current mirror circuit to mirror a reference current in a reference device circuit into the dummy device circuit to generate a mirrored current, and generates time control signals based on the mirrored current. Due to the same adaptation of the mirrored current to the size of a test device as the reference current, the time control signals are also adapted to the size of the test device. This addresses the problem of fixed time control signals arising from the use of a conventional RC relay circuit and enables the time control signals to change with the size of the test device as well as Process Voltage Temperature, thereby resulting in an effective reduction in average energy consumed in read operation.

Circuits for control of time for read operation, using a current mirror circuit to mirror a reference current into the dummy device and generates time control signals based on the mirrored current

A circuit for erasing data includes: a high voltage generation unit, adapted for generating an erasing signal; a first control unit, adapted for modifying the erasing signal to a first conduction control signal with a decreased voltage ascending speed; a second control unit, adapted for sending a second conduction control signal based on the first conduction control signal; a lift unit, adapted for lifting an output voltage for erasing data based on the first conduction control signal; a switch unit, adapted for forming an electrical access between the high voltage generation unit and the output end of the circuit for erasing data; and a reference current generation unit, adapted for providing a bias current to the first control unit and the second control unit. Under a circumstance that erasing effect of storage units is improved, area of a chip is relatively reduced by using the circuit for erasing data.

Circuit for erasing data

A circuit and a method for controlling operation voltage, and a storage device are provided. The circuit includes: a voltage boost unit adapted for: if receiving a first signal, performing a voltage boost process; and if receiving a second signal, stopping the voltage boost process; a voltage division unit including a plurality of different voltage division coefficients, adapted for performing a voltage division process; a comparison unit adapted for: comparing the divided voltage with a reference voltage; if the divided voltage is low, outputting the first signal; and if not, outputting the second signal; a control unit adapted for performing a descending switching operation on the voltage division coefficients; and an output unit. The establishing speed of the operation voltage is effectively controlled, and an effect on device power consumption and performance caused by the threshold voltage and variations of the threshold voltage in the working process is eliminated.

Circuit and method for controlling operation voltage, and storage device

A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Flash memory unit and memory array, and programming, erasing and reading method thereof

A voltage division circuit, a circuit for controlling operation voltage and a storage device are provided. The voltage division circuit includes: a receiving transistor; a transistor group including m transistors connected in series; n type-one switches, each of which includes three terminals, the first is connected with a drain of a former one and a source of a latter one of two adjacent transistors in the transistor group, the second is connected with ground, the third is adapted for receiving a timing control signal; and n+1 type-two switches, each of which includes three terminals, the first is connected with a source of a transistor in the transistor group, the second is adapted for outputting a divided voltage, and the third is adapted for receiving the timing control signal. The voltage division circuit can save chip area, and work properly under a condition that the voltage to be divided is low.

Voltage division circuit, circuit for controlling operation voltage and storage device

A rail-to-rail input hysteresis comparator includes: an input hysteresis comparator module, a transmission module, an output comparator, a switching signal module and a bias module. Compared to the conventional device, the rail-to-rail input hysteresis comparator of the present invention can turn off an output of the N-type input hysteresis comparator of the input hysteresis comparator module when the common mode input voltage is relatively low and turn off an output of the P-type input hysteresis comparator of the input hysteresis comparator module when the common mode input voltage is relatively high, thereby avoiding operating in a linear mode and hence achieving a stable CMRR.

Rail-to-rail input hysteresis comparator

A memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.

Memory and method of operating the same

An X-ray sensitive coating () for a flat panel direct conversion X-ray detector for medical or industrial imaging. A composite particle-in-binder (PIB) material () may contain X-ray photoconductive particles () such as PbO (lead monoxide) in a binder of polyimide (). This PIB material may be prepared in precursor paste form, and applied as a coating () onto a thin film transistor array () having a storage capacitor () at each pixel (). The coating () is cured, and an electrically conducting layer () is applied to the exposed surface of the coating (), to provide a bias voltage. X-ray photons striking the photoconductive particles () cause localized electrical conduction proportional to the number of photons. This charges respective capacitors () that provide image data input to a computer.

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Shanghai, China

Jun Xiao